Mentor Graphics VLSI CAD Tutorials

Transcription

1 VLSI Design Flow Using Mentor-Graphics Tools Mentor Graphics VLSI CAD Tutorials School of Engineering Santa Clara University Santa Clara, CA At the Design Center, School of Engineering, of Santa Clara University, we have developed a set of tutorials to help our students use Mentor Graphics Tools. The relationships of these tools to digital circuit design are outlined in the flowchart shown below. No previous knowledge of CAD tools is needed to use these tutorials. However, a certain level of knowledge of logic or circuit design is assumed. The tutorials have been used in undergraduate and graduate courses. We will be updating them as time permits and we look forward to your comments for improvement. (1 of 2)10/20/2007 4:02:23 PM

2 VLSI Design Flow Using Mentor-Graphics Tools If you have any suggestions, comments, or questions, please Last revision: February, (2 of 2)10/20/2007 4:02:23 PM

3 Schematic of an Inverter Circuit Using the Design Architect-IC (DA-IC) Santa Clara University Department of Electrical Engineering Date of Last Revision: September 22, 2006

4 Table of Contents 1. Objective Setup & Preparation Launching IC Studio Creating a project Opening icstudio and assigning the project a name Specifying Location Map Specifying Process files and other settings Creating a library and Cells...10 To Create a Library...10 Capturing a cell Schematic Entry Adding Components and Ports Wiring the components Adding Text / Changing Labels of Components Changing the Reference Number and Modifying other Properties Checking & Saving the Schematic Creating a Viewpoint Printing the Schematic Creating a Symbol...23

5 1. Objective This document contains a step-by-step tutorial for Mentor Graphics Design Architect tool to create the schematic of an inverter and then to generate its symbol. Simulation of the designed unit is covered in a separate tutorial.

6 2. Setup & Preparation The set of directives listed below is applicable to users of the Engineering Design Center at Santa Clara University. If you are working in a different environment please check with your system administrator. The steps below are necessary only for the first time to setup the Mentor Graphics environment by changing the settings in your.profile or.cshrc file. Add the following lines in your.profile: setup mentor alias swd= export MGC_WD=\ pwd\ Remember to execute $..profile If using C-shell add the following lines in your.cshrc: source /usr/local/scripts/setup.mentor csh alias swd= export MGC_WD=\ pwd\ Remember to execute $ source.cshrc

7 3. Launching IC Studio On the command line To Create a directory to contain your projects type: mkdir Tutorial To change the current directory to Tutorial type: cd Tutorial. To open ICSTUDIO type: icstudio&. This launches the ICStudio window shown below.

8 4. Creating a project To create a project the follow the three steps given below: 1. Opening icstudio and assigning the project a name On the ICStudio Window Click File -> New -> Project to create a new project. Click Next in the New project pop-up window Enter the Project name (e.g vlsi_tutorial) and the Project Location i.e., the name of the directory you created (e.g. Tutorial) to contain the project and click Next in the New project pop-up window.

9 2. Specifying Location Map On the next window that appears Click the Open Location Map Editor button. The Location Map Editor appears. To Add the design kit's standard cell libraries to the location map Click Edit Menu > Add Standard MGC Libraries pull down menu item. Following libraries will be automatically added. /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/mgc_ic_commlib /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/mgc_ic_comm_qs /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/mgc_ic_comm_rf /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/device_lib /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/generic_lib /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/sources_lib /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/mgc_ic_verilog /opt/mentor /app/2006.1_sun4os5/icflow_home/mgc_icstd_lib/mgc_ic_macrolib Add the MGC design kit to the location map Click Edit Menu > Add MGC Design Kit. Specify MGC Design Kit path as /opt/mentor /sol/adk2_5

10 The Library List editor looks as in the figure below. Click OK on the Library List Editor. Click Next on the New Project pop-up window. 3. Specifying Process files and other settings Click Open Settings Editor button. The Project tab of the Preferences dialog box appears. Load the process file (tsmc0xx). Process files are present in /opt/mentor /sol/adk2_5/technology/ic/process Load the following rules file to the project (tsmc0xx.rules) Rules files are present in /opt/mentor /sol/adk2_5/technology/ic/process o DRC rules file: tsmc0xx.rules o LVS rules file: tsmc0xx.calibre.rules o SDL rules file: tsmc0xx.accusim.rules o PEX rules file: tsmc0xx.calibre.rules NOTE: Select value for XX from 18, 25, and 35 depending on design requirement Fill in any other dialog box field to suit your project needs. Click OK on the Preferences dialog box.

11 Click Next on the New Project pop-up window. View the Summary to make sure all the information is correct. Click Finish.

12 5. Creating a library and Cells To Create a Library o Click New > Library. This opens the Create Library dialog box. o Enter the name of the library you want to create (e.g. Demo_Inverter). o Click OK. The library appears in the ICstudio library pane as well as in the location map. Capturing a cell To create a new Schematic cell: Select a library (e.g. Demo_Inverter) where you want a cell view to be created Click File > New > View. The Create New View dialog box opens. Enter the Cell Name (e.g. Inverter). If the cell does not exist, it is created. Specify the View Type as Schematic and click Finish

13 DA-IC will open automatically where in you can capture the required cell design NOTE: Standard devices and circuits are available in device lib and MACRO LIB present under IC Library. You will see an empty sheet in the Design Architect window. This sheet is where you will draw your schematic by placing the parts for your circuit and wiring them together. Click on Icon shown below to open Palette Menu. Palette menu will appear on right hand side of the window as shown in the figure below.

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15 6. Schematic Entry Now let s start drawing the schematic for the CMOS inverter. 1. Adding Components and Ports Select the parts for your schematic of the inverter by choosing from a library of components. To place transistors on the sheet In the palette menu which looks like the figure alongside, click on Device Lib. Select NMOS (4-pin) and place it on the sheet by clicking on the position you wish to place it. Similarly, select PMOS (4-pin) and place it on the sheet. Click BACK to go to the IC Library palette and click on Generic Lib. Place Portin, Portout, VDD and Ground on the sheet After placing all the components the schematic sheet looks as the one shown in the figure below.

16 2. Wiring the components To wire up the components Press function key F3 to wire up the components according to the circuit diagram in Figure. o Pressing F3 activates the wiring command. o Clicking on Cancel in the prompt bar or pressing Esc on your keyboard disables the wire command. Alternatively, wires can be added by using the schematic edit palette or from menu bar by clicking ADD > WIRE

17 3 Adding Text / Changing Labels of Components To change the value or text associated with any components, Point the cursor on that text/value and press SHIFT + F7 (Note You do not have to click/select the text or value. Just point the cursor on the value/text.) A display prompt bar appears at the bottom with the current value/text in the New Value box. Input the new name in this box and click OK. For example: To change the label NET of the PORTIN symbol to IN, i. Point the cursor on the text NET near the PORTIN symbol and press SHIFT + F7. ii. A display prompt bar appears at the bottom. Type IN in the New Value box and click OK.

18 Similarly change the label of PORTOUT symbol from NET to OUT. Now the schematic should look as shown in the figure. Note: You can also change values for the sizes of the transistors, instance names or any other text values associated with any component in the circuit. Alternatively, you can modify multiple properties of a device as explained in the next section.

19 4 Changing the Reference Number and Modifying other Properties To change the Reference Number automatically for both NMOS & PMOS, Highlight both the devices, click the right mouse button, and select Name Instance Auto. The reference numbers will be automatically changed by the tool. To change multiple properties of one device (e.g. NMOS) at a time, Highlight NMOS device, click right mouse button, and select Properties Edit.A new window will appear. In the box that appears, change following properties: INST: M1 (if not already changed before) L: 0.4u (drawn length of device: 0.4 micron) W: 1.2u (width of device: 1.2 micron) ASIM_MODEL: NCH (required for simulation) Note: Click on Apply button every time you change any value.

20 If you want to prepare a layout of your circuit and run LVS check, you also need to modify following properties. (If you just want to do simulations, you may skip these two properties) PHY_COMP : mn INSTPAR : $strcat("w=", W, " l=", L) Very important: Change the type for INSTPAR property to "expr". Also, you need to type this string carefully, as it is. Especially, do not forget the spaces in this string, as highlighted below for your reference. $strcat("w=", <space>w,<space> "<space>l=",<space> L) In case, there is no INSTPAR property (or any other required property) listed in the multiple properties table of a device, insert it in the last blank row of the table. Similarly, select the PMOS and change the properties as follows: INST: M2 (if not already changed before) L: 0.4u (drawn length of device: 0.4 micron) W: 3.6u (width of device: 3.6 micron)

21 ASIM_MODEL: PCH (required for simulation) PHY_COMP: mp (required for LVS) INSTPAR: $strcat("w=", W, " l=", L) ( required for LVS) Final schematic will look like as shown in the figure below.

22 7. Checking & Saving the Schematic Click Check& Save from the schematic edit palette or and save your sheet. in the menu bar to check Note: If your sheet does not pass check, you cannot simulate the design. Check the log if errors are listed. If your sheet passes all checks you will get the following message in the message pane: Note: "Inverter/schematic/sheet1" passed check Note: Version 1 of sheet $Demo_Inverter/default.group/logic.views/Inverter/schematic/sheet1 has been written

23 8. Creating a Viewpoint To prepare for simulation in DA_IC, a Design Viewpoint needs to be created. The tool automatically creates the viewpoint when you enter into simulation mode. i. Click on simulation from the schematic edit palette on the RHS Or Click on on the LHS Vertical Icon Bar to enter the simulation mode. ii. Click OK to accept default options and to create a viewpoint. You will use the viewpoint during layout of the circuit. iii. Click on end simulation in the Schematic_sim palette or on the LHS Vertical Icon Bar to end the simulation and get back in schematic edit mode.

24 9. Printing the Schematic To print the schematic Click File -> Print Enter laser in the Printer name box. Do not modify any other settings. Click OK.

25 10. Creating a Symbol Hierarchical design allows you to instantiate lower level cells (circuits) into upper level cells to create a tree structure. Since, at higher levels, we really don't need to see the detailed transistor-level description of the base cells, we create symbols for them. Also we will use this symbol to perform various simulations on the circuit in the simulation tutorial. Make sure that the schematic is checked & saved before making the symbol. To generate a Symbol Automatically: 1. From the menu bar select Tools -> Generate Symbol 2. In the Generate symbol dialog box, a. Click Choose shape. Notice that variety of shapes are available for the symbol and one can choose any of these shape that best describes the circuit. b. Select Buffer and click OK. c. Do not change any other options in the dialog box and click the OK button to generate a symbol for the cell. 3. The symbol is created automatically and displayed in a new window as shown below. Do not forget to save this symbol by selecting Check & Save from the symbol_draw palette on the right hand side. You can now use this symbol in other schematics. You can edit symbol by selecting different shapes from right hand palette.

26 The symbol generated for the given Inverter is shown in the figure below.

27 How do I do the simulation? ** ** Please refer to the tutorial for Simulation of Inverter Circuit

28 Simulation for an Inverter Circuit Using the Design Architect-IC (DA-IC) Santa Clara University Department of Electrical Engineering Date of Last Revision: September 22, 2006

29 Table of Contents 1. Objective Basic Test Circuit Creation...4 Adding Instance to the test circuit...4 Setting up the simulation parameters...5 Setting up the simulator / Viewer DC Analysis...8 Editing and simulating the test circuit...8 Setting up the simulation parameters...9 Executing the simulation setup...10 Viewing the results using EZWave viewer...10 Printing the plots: DC Operating Point Analysis...13 Editing and simulating the test circuit...13 Setting up the simulation parameters...13 Viewing the results using EZWave viewer...14 Power consumption of the circuit Transient Analysis...17 Editing and simulating the test circuit...17 Setting up the simulation parameters...18 Setting up the signals to be probed...19 Executing the simulation setup...19 Viewing the results using EZWave viewer AC Analysis...22 Editing and simulating the test circuit...22 Setting up the simulation parameters...23 Setting up the signals to be probed...23 Executing the simulation setup...24 Viewing the results using EZWave viewer...24

30 1. Objective This Tutorial contains a step-by-step procedure for simulating an inverter circuit in the Mentor Graphics Design Architect tool. It covers DC Analysis, Transient Analysis, DC Operating Point Analysis and AC Analysis simulation of the inverter circuit. This tutorial assumes that the schematic of the inverter is already created. For help with creating schematic and symbol, please refer to Schematic Entry tutorial for Inverter Circuits.

31 2. Basic Test Circuit Creation Open icstudio from the command prompt as mentioned in the Schematic Entry tutorial Create a new view in the created library (Demo_Inverter) and name it as test_inverter with view type as Schematic. We will use this sheet to create basic test circuit required for the simulations. Adding Instance to the test circuit A new schematic entry sheet opens in DA-IC. In this test_inverter sheet, i. Add an inverter symbol (that you generated in the schematic entry tutorial) click Add Instance from schematic_edit palette on RHS. ii. In the Choose Symbol popup window, click Browse, navigate and select inverter and click OK. Place this symbol of the inverter in the sheet as shown in the figure below.

32 iii. Add a PORTIN, PORTOUT, VDD and Ground from Generic Lib iv. Name the ports as INPUT & OUTPUT respectively and wire them to the IN and OUT pins of the inverter symbol as shown in the figure. v. Add a DC source by selecting IC_Library Sources Library DC. vi. Highlight the DC source, right click mouse, Properties Edit to modify the voltage value of the source from 1V to 3.3V. vii. Connect the positive node of the DC source to VDD symbol and negative terminal to the Ground symbol. The circuit should look like as shown in the figure below. viii. Click Check & Save the sheet. And then click on simulation from the schematic_edit palette on the RHS to enter the simulation mode. A popup window appears with a Warning message that the schematic will be closed. Click OK to accept default options. Setting up the simulation parameters In the simulation mode (schematic_sim palette), Click the right mouse button Lib/Temp/Inc Library.

33 Type /opt/mentor /sol/adk2_5/technology/ic/models/tsmc035.mod in Library path box and click OK. This includes the TSMC0.35 micron BSIM model for the simulations. The screen now would look like the figure included below Setting up the simulator / Viewer In the simulation mode (schematic_sim palette), Click Session -> Simulator / Viewer. Select Eldo under Simulator and EZwave under Viewer and click OK.

34 Click on check & save and then click on end simulation to get back in schematic_edit mode.

35 2. DC Analysis For DC analysis, we sweep the input voltage from 0V to 3.3V and view its effect on the output. Editing and simulating the test circuit 1) Open the test_inverter sheet that you had created with the symbol of your inverter and make sure that you are in schematic_edit mode. 2) Add a DC voltage source between the INPUT pin and Ground as shown in the following figure. Name this source as VIN. (Note that the value of the DC voltage source is 1V, by default. For DC analysis, this value does not matter and so you can leave it as it is!) 3) Click Check & save the sheet and then enter the simulation mode by clicking on simulation from the schematic_edit palette on RHS. Click OK to accept default options in the Warning popup window appeared.

36 Setting up the simulation parameters On the schematic_sim palette: Click on Lib/Temp/Inc Library to make sure that /opt/mentor /sol/adk2_5/technology/ic/models/tsmc035.mod appears in library path box and click OK. Click Setup Analyses. In the Setup Simulation Analysis window that appears, select DC and click on Setup associated with DC. In the Setup box that appears, select Source and select VIN for Voltage source, put 0 in the start field, 3.3 in the stop field and 0.01 in the step field and then click OK. Select the wires connected to INPUT and OUTPUT pins on the sheet. Click Setup Outputs Save from the Menu Bar. This opens the Set Plots dialog box. Select Voltage for the Plot type and from Advanced tab select DC for the Analysis type and click OK. Setup Difference Plot window will appear. Select individually for the plot type.

37 Executing the simulation setup On the schematic_sim palette: Click Execute Netlist. This opens up a new window that starts netlister. Check the netlist created for any errors. If there are any errors, correct them before proceeding further. Else close the window by pressing Enter key. Click Execute Run Eldo. This starts Eldo in a new shell window and it may take few seconds before the simulation is complete. You may scroll down the window to see the DC simulation results. Press Enter key to close the Shell Window. Viewing the results using EZWave viewer To view the results of your DC analysis in EZWave, do the following: On the schematic_sim palette: Click Results -> View Waves. A new window will open with waveform plot as shown below.

38 Printing the plots: To Print your waveform: Click File -> Print. Type `laser` for the printer name & Click OK.

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40 3. DC Operating Point Analysis In this section, you will find the DC operating point of several nodes in the circuit and look at the transfer function of the input. Editing and simulating the test circuit Open the test_inverter sheet that you had created with the symbol of your inverter and make sure that you are in schematic edit mode. The setup is exactly similar to the DC Analysis setup and we will carry out DCOP analysis for input voltage of 1V. Add a DC voltage source between the INPUT pin and ground as shown in the following figure. Name this source as VIN and make sure that its value is 1V. Setting up the simulation parameters On the schematic_sim palette: Click Setup Analyses. Select DCOP in the dialog box that appears, and then click OK.

41 Click Execute Netlist and then Run ELDO. Viewing the results using EZWave viewer The next step is to view the results of your simulation run. To see all the DC voltages and currents in your schematic, Click Results DCOP Add monitor All Nets Voltages Again click DCOP Add monitor All Pins - Current

42 Current and Voltage values at various nodes will be displayed as shown in the above figure. Alternately, you can select voltages or current option, if you want to see only voltages or currents. Power consumption of the circuit The power consumption of the circuit for the given operating point is calculated during the DCOP simulation. To check it out, Click on Results ASCII Files, right click mouse button View Log. Scroll down in the log window to find the information about the power consumption as shown in the figure below:

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44 4. Transient Analysis In this section, you will provide a pulse at the input and view the input & output waveforms. Editing and simulating the test circuit Open the test_inverter sheet that you had created with the symbol of your inverter and make sure that you are in schematic_edit mode. Add a PULSE voltage source between the INPUT pin and Ground as shown in the following figure. Name this sourse as VIN and change the attributes as: Initial_value = 0, Pulse_value = 3.3V, Delay = 0, t_rise = 1ns, t_fall = 1ns, Width = 20ns Period = 50ns ( You can use either SHIFT + F7 to change these values one at a time or you may change all the values by first selecting the PULSE voltage source and then Right clicking the mouse to select Properties Edit. Make sure you click Apply after changing each parameter.)

45 Check & save the sheet and then enter the simulation mode by clicking on simulation from the schematic_edit palette on RHS. Click OK to accept default options in the Warning popup window appeared. Setting up the simulation parameters On the schematic_sim palette: Click on Lib/Temp/Inc -> Library to make sure that /opt/mentor /sol/adk2_5/technology/ic/models/tsmc035.mod appears in library path box and click OK. Click Setup -> Analyses. In the Setup Simulation Analysis window that appears, select Transient and click on Setup associated with it. In the Setup box that appears type 0.1nS in the Output Start Time, 300nS in the Stop Time field and 1nS in Max Time Step field. Then click OK.

46 Setting up the signals to be probed You need to setup the signals to be plotted and probed in order to view the results after simulation. To view the input and output waveforms of your inverter, Highlight INPUT and OUTPUT wires on the sheet Click Setup Wave Outputs. Select Voltage for Plot Type; check TRAN for Analysis type in Advanced and then click OK Setup Difference Plot window will appear select individually for the plot type. Executing the simulation setup Click Execute -> Netlist Click Execute -> Run ELDO Viewing the results using EZWave viewer On the Schematic_sim palette: Select Results ASCII Files from the palette menu to see netlist and log files.

47 Click Results View Waves. Waveform window will appear with both input and output waveforms mixed into each other as shown in the figure To view the Input & Output waveforms separately, select V (OUTPUT) from Currently Open database test_inverter_eldonet TRAN V (OUTPUT) and click delete and then right click on V (OUTPUT) and click PLOT. Two different plots as shown below will appear.

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49 5. AC Analysis In this section, you will run AC analysis and trace and measure your results. In AC Analysis, the input signal is swept over a range of frequencies. First you have to disable the earlier Transient setup that you applied during the transient analysis. Follow these steps to do AC Analysis on the circuit Editing and simulating the test circuit 1) Open the test_inverter sheet that you had created with the symbol of your inverter and make sure that you are in schematic_edit mode. 2) Add an AC voltage source between the INPUT pin and Ground as shown in the following figure. Name this source as VIN. 3) Change the value of Mag field to 3.3 V 4) Click Check & save the sheet and then enter the simulation mode by clicking on simulation from the schematic_edit palette on RHS. Click OK to accept default options in the Warning popup window appeared.

50 Setting up the simulation parameters On the schematic_sim palette: Click Setup -> Analysis. Check AC and click on the Setup box associated with it. Select the Decade button for Sweep type. For this circuit you will perform an AC sweep of input frequency from 1 to 10G. Enter these values in the Start Freq and Stop Freq respectively. Click OK Setting up the signals to be probed You need to setup the signals to be plotted and probed in order to view the results after simulation. To view output waveforms of your inverter, Highlight INPUT and OUTPUT wires Click Setup Output Save Selected components tab. Check AC, select DB-Phase, and then click OK. Setup Difference Plot window will appear select individually for the plot type.

51 Executing the simulation setup Click Execute -> Netlist Then click Execute -> Run ELDO. Viewing the results using EZWave viewer Select Results -> ASCII Files -> View Log from the palette menu to see netlist. Make sure it does not show any ERROR. To view the results of your AC analysis, invoke the EZWave viewer by clicking on Results -> View Waves Finally I understand this stuff!

52 Layout and Layout Verification of an Inverter Circuit Santa Clara University Department of Electrical Engineering Revised by Arpita Sharan Under Guidance of Dr Samiha Mourad & Dr Shoba Krishnan Date of Last Revision: October 31, 2006 Copyright 2006

53 Table of Contents 1. Objective Setup & Preparation Launching IC Studio...6 _Toc Opening the project Opening icstudio and opening the project Opening Layout Cell Drawing the Layout Actual Inverter Layout Making Ports Save / Reserve Cell Verifying the Layout Design rules (DRC) Verifying the Layout Vs Schematic (LVS)...27 Copyright

54 1. Objective This tutorial shows a step-by-step procedure for creating a custom (manual) layout of the inverter schematic that you created in Schematic entry tutorial. The schematic and the final layout are as shown in the figure below. It also helps you verify your layout by using the IC Station physical verification tools Calibre to perform simple DRC (Design Rule Check), and LVS (Layout Vs Schematic) check. Copyright

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56 2. Setup & Preparation The set of directives listed below is applicable to users of the Engineering Design Center at Santa Clara University. If you are working in a different environment please check with your system administrator. The steps below are necessary only for the first time to setup the Mentor Graphics environment by changing the settings in your.profile or.cshrc file. Add the following lines in your.profile: setup mentor alias swd= export MGC_WD=\ pwd\ Remember to execute $..profile If using C-shell add the following lines in your.cshrc: source /usr/local/scripts/setup.mentor csh alias swd= export MGC_WD=\ pwd\ Remember to execute $ source.cshrc Copyright

57 3. Launching IC Studio On the command line To Create a directory to contain your projects type: mkdir Tutorial To change the current directory to Tutorial type: cd Tutorial. To open ICSTUDIO type: icstudio&. This launches the ICStudio window shown below. Copyright

58 4. Opening the project To create a project the follow the three steps given below: 1. Opening icstudio and opening the project On the ICStudio Window Click File -> Open -> Project to create a new project. Enter the Project name (e.g vlsi_tutorial) and the Project Location Click Open in the Open Project pop-up window 2. Opening Layout Cell Right click on the name of the Schematic you entered (eg.; Inverter) and click New View. Select View Type as Layout. Click Finish. Copyright

59 The following window will open wherein you can draw your schematic layout. Copyright

60 Note: Before you make any changes to your work, make sure your work is in the 'Edit' mode. Copyright

61 5 Drawing the Layout For this Click File> Enable editing > Current Context Copyright

62 1. Actual Inverter Layout Now that we are familiar with basic editing commands, lets start with the layout of the inverter. Note:In the working space, one unit is equal to one Lambda (l). (refer to the cursor coordination on the window frame). If you follow the Lambda rules for TSMC0.35u technology, the smallest feature size will be 2l = 0.4u (for poly width and contact size). Therefore we have 1l = 0.2micron To Create the NMOS with 0.4 micron length and 1.2 micron width: o Click CONTACT_TO_ACTIVE (48) on RHS of the window. o Click Draw Rectangle on the LHS of the window and draw a 2lX2l square of layer 48. o Next create 6l x 6l METAL1 Square for Contact. The result should look like in the following figure. Select both the shapes and Click Edit> Copy> Selected Copyright

63 Next Click Edit> Paste Place all these shapes beside the original ones with 4l spacing. They are source and drain contacts. Create 6l x 16l ACTIVE (active area) to cover exactly source and drain metal contact. Next To Make the PMOS: o Click CONTACT_TO_ACTIVE (48) on RHS of the window. o Click Draw Rectangle on the LHS of the window and draw a 2lX2l square of layer 48. o Next create 18l x 6l METAL1 Rectangle for Contact Note: Distance between the NMOS and the PMOS should be at least 13l Select all the shapes and Click Edit> Copy> Selected Next Click Edit> Paste Place all these shapes beside the original ones with 4l spacing. They are source and drain contacts. Create 18l x 16l ACTIVE (active area) to cover exactly source and drain metal contact. Copyright

64 Next create a 41L X 2L poly between the drain and source contacts for NMOS and PMOS. Add 22l x 20l P_PLUS_SELECT for PMOS and 10l x 20l N_PLUS_SELECT for NMOS. The spacing between N_PLUS_SELECT and P_PLUS_SELECT should be kept at least 9l for correct NWELL and PWELL spacing as shown below. Copyright

65 Note: It is always better to add as many CONTACTS as possible to reduce the contact resistance. So add 3 contacts in the Source area of PMOS (with 3l distance in between the contacts) and 4 contacts in the drain area of PMOS (with 2l distance in between the contacts) as shown in the adjacent figure. Note: As per the design rules of TSMC0.35, minimum separation between two contacts should be 3l. Add 30l x 28l NWELL for PMOS and 18l x 28l PWELL for NMOS. The spacing between NWELL and PWELL should be at least 1l. Copyright

66 Add METAL1: to form Vdd (power wire) and GND (ground wire). Note that METAL1 should have at least 3l width and 3l spacing (METAL1 to METAL1 spacing). Now, connect PMOS-source to Vdd and that of NMOS to GND with METAL1. (Use 'Notch For this select the shape you want to notch or connect and click Edit-> Notch Use your Left Mouse Button to alter Move the shape as desired and when you are done press Escape) Connect the drains of both transistors by METAL1, to get OUTPUT net of the inverter. The figure when you have notched the VDD, GND and POLY would look as under: Copyright

67 To have well ties in layout-- continue with the following steps: Use Notch to extend the left hand side edges of WELL, ACTIVE (active area), and METAL1 of the SOURCES of both NMOS & PMOS by 8l. Add N_PLUS_SELECT inside NWELL and P_PLUS_SELECT inside PWELL. Also add CONTACT to both N_PLUS_SELECT and P_PLUS_SELECT. Notice that the PMOS's source is connected to VDD and NMOS's source is Connected to the GND. By connecting the body of the wells to the sources through metal1 we are connecting the NWELL to VDD and PWELL to the GND. The final figure when you have notched the VDD, GND and POLY would look as under Copyright

68 6. Making Ports From main menu bar, select Connectivity -> Port -> Make Port: For the Port Name, enter VDD. Make sure the Port Type is Signal and Direction is in. Then click OK Repeat the steps above to assign GND (Metal1), IN (Poly) and OUT (Metal1) ports. Note:'GND' and 'IN' are of 'in' Direction while 'OUT' is of 'out' Direction. Now, you have finished the layout. It's time to save your work! Copyright

69 7. Save / Reserve Cell To save Cell: Select, from main Menu Bar, File -> Cell -> Save Cell Note: After you save your work, the system will automatically set your work to 'Read-Only' mode. To set your work to 'Editable' mode, Click File> Enable Editing>Current Context Copyright

70 8. Verifying the Layout Design rules (DRC) Click Tools > Calibre > Run DRC The following Window pops up Enter the Path to Calibre as: /opt/mentor /app/calibre/sol/ss5_cal_2006.2_38.31 Copyright

71 When you are done the following window pops up: Copyright

72 The DRC tool stores results as shown under. Click on Outputs to see the location where the tool stores the result Copyright

73 Click Run DRC Copyright

74 The Calibre DRC RVE should say No (Zero) Results in 81 Checks as under If you do not have any DRC errors the window would look like: Copyright

75 In case you have errors in your DRC the window would look as under. Click on the RED marked Squares and get to the errors. Correct them till you get No results Copyright

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78 9. Verifying the Layout Vs Schematic (LVS) Click Tools > Calibre > Run LVS The following window pops up: Specify the Layout netlist path and Click Run LVS Copyright

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80 The LVS if it is correct would give you a result as under Copyright

81 Copyright