Counters. Counter Types. Variations. Modulo Gray Code BCD (Decimal) Decade Ring Johnson (twisted ring) LFSR
|
|
- Cora Campbell
- 6 years ago
- Views:
Transcription
1 CE 1911 Counters
2 Counter Types Modulo Gray Code BC (ecimal) ecade Ring Johnson (twisted ring) LFSR Variations Asynchronous / Synchronous Up/own Loadable 2 tj
3 Modulo-n (n = a power of 2) Asynchronous Count in binary Mod-16 b0 b1 b2 bn-1 clk_in rstb 3 tj
4 Modulo-n (n = a power of 2) Synchronous Count in binary J J J b0 b1 b2 bn-1 J K K K K clk_in rstb 4 tj
5 Modulo-m (m not a power of 2) Synchronous Has m states Mod-5 Mod n counter with logic to synchronous clear the Flip Flops when last state is reached RST n ecode Logic 5 tj
6 Gray Code Synchronous Only 1 bit changes at a time > 000 N bit state machine with next state logic Mod-n counter with output logic n Output Logic Out 6 tj
7 BC Binary Coded ecimal Synchronous Outputs limited to 0-9 Mod-m counter with m = 10 Last state (9) also enables next clock to increment the next digit 7 tj
8 ecade Synchronous 10 output states Not necessary to be 0-9 n bit state machine with next state logic Mod-n counter with output logic Last state (?) also enables next clock to increment the next digit 8 tj
9 Ring Synchronous Any number of states (1 FF / state) Rotate a single 1 or single 0 around in a loop or Note no 0 state otherwise nothing to rotate Shift register with 0 tied to last bit and 1 bit set or reset SETB b0 b1 b2 clk_in rstb 9 tj
10 Johnson (twisted ring) Synchronous Any number of states (1FF / 2 states) Rotate a pattern in a loop Shift register with 0 tied to last bit b0 b1 b2 clk_in rstb 10 tj
11 LFSR (Linear Feedback Shift Register) Synchronous pseudo random pattern generator Shift register with 0 tied to feedback logic designed to create a specific pattern Feedback Logic s b0 b1 b2 clk_in rstb 11 tj
12 Up/own capability Twice as many state transitions Loadable Logic to force desired FFs into set or reset state 12 tj
13 Counter - 4 bit nbitcounter.vhdl created 2/29/17 tj rev 0 n bit up-counter example Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nbitcounter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of nbitcounter is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 13 tj
14 Counter mod 9 mod9counter.vhdl created 3/16/17 tj rev 0 mod 9 counter example Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mod9counter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of mod9counter is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then if(bout_sig = 8) then bout_sig <= (others => '0'); else bout_sig <= bout_sig + 1; end if; end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 14 tj
15 Counter mod-9 15 tj
16 Counter mod 9b mod9counterb.vhdl created 3/16/17 tj rev 0 mod9 counter example B Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mod9counterb is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of mod9counterb is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; end if; check for terminal state if(bout_sig = 9) then bout_sig <= (others => '0'); end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 16 tj
17 Counter mod-9b 17 tj
18 Tick Counter tickcounter.vhdl created 3/16/17 tj rev 0 tick counter example Inputs: rstb, clk Outputs: ticka, tickb library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tickcounter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; ticka : out std_logic; tickb : out std_logic ); end entity; architecture behavioral of tickcounter is internal signals - for doing math signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; if(bout_sig = 5) then ticka <= '1'; else ticka <= '0'; end if; if(bout_sig = 7) then tickb <= '1'; else tickb <= '0'; end if; end if; end process; Output logic end behavioral; increment count ticka detect (6th clk) tickb detect (8th clk) 18 tj
19 Tick Counter 19 tj
Quartus Counter Example. Last updated 9/6/18
Quartus Counter Example Last updated 9/6/18 Create a logic design from start to a DE10 implementation This example uses best design practices This example is not about creating HDL The HDL code will be
More informationIn our case Dr. Johnson is setting the best practices
VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry
More informationSequential Statement
Sequential Statement Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential
More informationCS/EE Homework 7 Solutions
CS/EE 260 - Homework 7 Solutions 4/2/2001 1. (20 points) A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111,
More informationSequential Logic - Module 5
Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the
More informationMAX 10. Memory Modules
MAX 10 Memory Modules Three types of on-chip memory FF based memory embedded in the LEs Most efficient for very small memories Compiler driven Embedded SRAM block 8K bits + 1024 parity bits (9216b) MAX
More informationNanosistemų programavimo kalbos 5 paskaita. Sekvencinių schemų projektavimas
Nanosistemų programavimo kalbos 5 paskaita Sekvencinių schemų projektavimas Terminai Combinational circuit kombinacinė schema (be atminties elementų) Sequential circuit nuosekli (trigerinė, sekvencinė)
More informationVHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state
More informationEL 310 Hardware Description Languages Midterm
EL 3 Hardware Description Languages Midterm 2 3 4 5 Total Name: ID : Notes: ) Please answer the questions in the provided space after each question. 2) Duration is minutes 3) Closed books and closed notes.
More information[VARIABLE declaration] BEGIN. sequential statements
PROCESS statement (contains sequential statements) Simple signal assignment statement
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6
DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine:
More informationCSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014
CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not
More informationLecture 4: Modeling in VHDL (Continued ) EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 4: Modeling in VHDL (Continued ) Sequential Statements Use Process process (sensitivity list) variable/constant declarations Sequential Statements end process; 2 Sequential
More informationSEQUENTIAL STATEMENTS
SEQUENTIAL STATEMENTS Sequential Statements Allow to describe the behavior of a circuit as a sequence of related events Can be used to model, simulate and synthesize: Combinational logic circuits Sequential
More informationECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University
ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential
More informationCOE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14
COE 405, Term 062 Design & Modeling of Digital Systems HW# 1 Solution Due date: Wednesday, March. 14 Q.1. Consider the 4-bit carry-look-ahead adder (CLA) block shown below: A 3 -A 0 B 3 -B 0 C 3 4-bit
More informationAbi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationFSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also
More informationCSE 260 Introduction to Digital Logic and Computer Design. Exam 1 Solutions
CSE 6 Introduction to igital Logic and Computer esign Exam Solutions Jonathan Turner /3/4. ( points) raw a logic diagram that implements the expression (B+C)(C +)(B+ ) directly (do not simplify first),
More informationIn this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and
In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing async circuit 4. Inference of basic memory elements 5. Simple
More informationVHDL Examples Mohamed Zaky
VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1 Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A
More informationClocked Sequential System Design. Multiply Example
Clocked Sequential System Design Example 1 Multipliers (Gradeschool, Modified Gradeschool) Multiply Example (185) (215) 00000000 00000000 ------ 1001101101011111 (39775) 1 0000000000000000
More informationECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
More informationECEU530. Homework 4 due Wednesday Oct 25. ECE U530 Digital Hardware Synthesis. VHDL for Synthesis with Xilinx. Schedule
EEU530 EE U530 igital Hardware Synthesis Lecture 11: Prof. Miriam Leeser mel@coe.neu.edu October 18, 2005 Sequential Logic in VHL Finite State Machines in VHL Project proposals due now HW 4 due Wednesday,
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION
More informationSummary of FPGA & VHDL
FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 13 Counters Overview Counters are important components in computers The increment or decrement by one
More informationECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. Behavioral Design Style: Registers & Counters.
ECE 55 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks Required reading P. Chu, RTL Hardware esign using VHL Chapter 5.1, VHL Process Chapter 8, Sequential Circuit esign: Principle
More informationCOVER SHEET: Total: Regrade Info: 5 (14 points) 7 (15 points) Midterm 1 Spring 2012 VERSION 1 UFID:
EEL 4712 Midterm 1 Spring 2012 VERSION 1 Name: UFID: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer
More informationTiming in synchronous systems
BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHL-code that introduces latches andf flip-flops Initialization of registers Mealy- and Moore machines
More informationLuleå University of Technology Kurskod SMD152 Datum Skrivtid
Luleå University of Technology Kurskod SMD152 Datum 2003-10-24 Skrivtid 9.00 13.00 1 Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics
More informationPart 4: VHDL for sequential circuits. Introduction to Modeling and Verification of Digital Systems. Memory elements. Sequential circuits
M1 Informatique / MOSIG Introduction to Modeling and erification of Digital Systems Part 4: HDL for sequential circuits Laurence PIERRE http://users-tima.imag.fr/amfors/lpierre/m1arc 2017/2018 81 Sequential
More informationVHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents
VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for
More informationentity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority;
Примери Приоритетен кодер library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority; architecture Behavioral
More informationThe University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #6 Solution
5.3(a)(2), 5.6(c)(2), 5.2(2), 8.2(2), 8.8(2) The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 25 Homework #6 Solution 5.3 (a) For the following SM chart:
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 2.2.2: VHDL-3 Liang Liu liang.liu@eit.lth.se 1 Outline Inference of Basic Storage Element Some Design Examples DFF with enable Counter Coding Style:
More informationSign here to give permission for your test to be returned in class, where others might see your score:
EEL 4712 Midterm 2 Spring 216 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)
More informationConcurrent & Sequential Stmts. (Review)
VHDL Introduction, Part II Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer Academic Publishers, 2001, ISBN 0-7923-7439-
More informationThe University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution Spring 2016
The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam Solution Spring 2016 1. (15 points) Write a VHDL function that accepts a std_logic_vector of arbitrary length and an integer
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 6 Combinational and sequential circuits
EE 459/5 HL Based igital esign with Programmable Logic Lecture 6 ombinational and sequential circuits Read before class: hapter 2 from textbook Overview ombinational circuits Multiplexer, decoders, encoders,
More informationPollard s Tutorial on Clocked Stuff in VHDL
Pollard s Tutorial on Clocked Stuff in VHDL Welcome to a biased view of how to do register type of stuff in VHDL. The object of this short note is to identify one way to easily handle registered logic
More informationContents. Chapter 9 Datapaths Page 1 of 28
Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for
More informationDESIGN AND IMPLEMENTATION OF MOD-6 SYNCHRONOUS COUNTER USING VHDL
Arid Zone Journal of Engineering, Technology and Environment. August, 2013; Vol. 9, 17-26 DESIGN AND IMPLEMENTATION OF MOD-6 SYNCHRONOUS COUNTER USING VHDL Dibal, P.Y. (Department of Computer Engineering,
More informationDesign Problem 3 Solutions
CSE 260 Digital Computers: Organization and Logical Design Jon Turner Design Problem 3 Solutions In this problem, you are to design, simulate and implement a sequential pattern spotter, using VHDL. This
More informationControl Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed
More informationField Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
More informationVHDL in 1h. Martin Schöberl
VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 2.2.2: VHDL-3 Liang Liu liang.liu@eit.lth.se 1 Outline Inference of Basic Storage Element Some Design Examples DFF with enable Counter Coding Style:
More informationDesign Problem 4 Solutions
CSE 260 Digital Computers: Organization and Logical Design Design Problem 4 Solutions Jon Turner The block diagram appears below. The controller includes a state machine with three states (normal, movecursor,
More informationInferring Storage Elements
Inferring Storage Elements In our designs, we usually use flip-flops as our storage elements. Sometimes we use latches, but not often. Latches are smaller in size, but create special, often difficult situations
More informationProblem Set 10 Solutions
CSE 260 Digital Computers: Organization and Logical Design Problem Set 10 Solutions Jon Turner thru 6.20 1. The diagram below shows a memory array containing 32 words of 2 bits each. Label each memory
More informationSchedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November
More informationHDL. Hardware Description Languages extensively used for:
HDL Hardware Description Languages extensively used for: Describing (digital) hardware (formal documentation) Simulating it Verifying it Synthesizing it (first step of modern design flow) 2 main options:
More informationSequential Logic Blocks
Sequential Logic Blocks Output of sequential blocks depends on present state as well as on past state. Sequential circuits work with a reference which is clock. A clock signal can be of any duty cycle,
More informationVerilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered
More informationFinite State Machines (FSM) Description in VHDL. Review and Synthesis
Finite State Machines (FSM) Description in VHDL Review and Synthesis FSM Review A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM). Finite
More informationVHDL for Modeling - Module 10
VHDL for Modeling Module 10 Jim Duckworth, WPI 1 Overview General examples AND model Flip-flop model SRAM Model Generics DDR SDRAM Model Constraints Metastability Block Statements Just for reference Jim
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs
IGITAL LOGIC SIGN VHL Coding for FPGAs SUNTIAL CIRCUITS Unit 5 Asynchronous sequential circuits: Latches Synchronous circuits: flip flops, counters, registers. Testbench: Generating stimulus COMBINATIONAL
More informationThe Virtex FPGA and Introduction to design techniques
The Virtex FPGA and Introduction to design techniques SM098 Computation Structures Lecture 6 Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL
More informationCOVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)
EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
More informationChapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and
More informationLatch Based Design (1A) Young Won Lim 2/18/15
Latch Based Design (1A) Copyright (c) 2015 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationChapter 5 Registers & Counters
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course
More informationCOVER SHEET: Total: Regrade Info: Problem#: Points. 7 (14 points) 6 (7 points) 9 (6 points) 10 (21 points) 11 (4 points)
EEL 4712 Midterm 3 Spring 2013 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
More informationCprE 583 Reconfigurable Computing
Recap 4:1 Multiplexer CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #18 VHDL for Synthesis I LIBRARY ieee
More informationProgrammable Logic. Simple Programmable Logic Devices
Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements
More informationVHDL Simulation. Testbench Design
VHDL Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus of UUT inputs algorithmic
More informationECOM 4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. Counters Page 2 Counters - special name of any clocked sequential circuit
More informationECE 459/559 Secure & Trustworthy Computer Hardware Design
ECE 459/559 Secure & Trustworthy Computer Hardware Design VHDL Overview Garrett S. Rose Spring 2016 Recap Public Key Encryption (PKE) RSA (Rivest, Shamir and Adelman) Encryption Advanced Encryption Standard
More informationDESCRIPTION OF DIGITAL CIRCUITS USING VHDL
DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,
More informationEEL 4712 Digital Design Test 1 Spring Semester 2007
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. COVER SHEET: Problem: Points: 1 (15 pts) 2 (20 pts) Total 3 (15 pts) 4 (18 pts)
More informationCodec. WM8731 Audio Codec
Codec WM8731 Audio Codec Codec Coder / Decoder Audio, Video Compression/decompression signal coding 2 tj WM8731 3 tj WM8731 Data Path Basic Connection 4 tj WM8731 Data Path Basic Timing 5 tj WM8731 Data
More informationDigital Design: An Embedded Systems Approach Using VHDL
igital esign: An Embedded Systems Approach Using Chapter 4 Sequential Basics Portions of this work are from the book, igital esign: An Embedded Systems Approach Using, by Peter J. Ashenden, published by
More informationVHDL Modeling Behavior from Synthesis Perspective -Part B - EL 310 Erkay Savaş Sabancı University
VHDL Modeling Behavior from Synthesis Perspective -Part B - EL 310 Erkay Savaş Sabancı University 1 The Wait Statement Syntax wait until condition; Different forms wait until(clk event and clk = 1 ); wait
More information3 Designing Digital Systems with Algorithmic State Machine Charts
3 Designing with Algorithmic State Machine Charts An ASM chart is a method of describing the sequential operations of a digital system which has to implement an algorithm. An algorithm is a well defined
More informationCSE 260 Digital Computers: Organization and Logical Design. Exam 2. Jon Turner 3/28/2012
CSE 260 Digital Computers: Organization and Logical Design Exam 2 Jon Turner 3/28/2012 1. (15 points). Draw a diagram for a circuit that implements the VHDL module shown below. Your diagram may include
More informationECE 545 Lecture 11 Addendum
ECE 545 Lecture 11 Addendum Controllers for Keccak_F and AES George Mason University ECE 448 FPGA and ASIC Design with VHDL Keccak_F 1600 din start done Keccak_F rst 1600 dout ready Note: Bold line represents
More informationEE 231 Fall EE 231 Homework 8 Due October 20, 2010
EE 231 Homework 8 Due October 20, 20 1. Consider the circuit below. It has three inputs (x and clock), and one output (z). At reset, the circuit starts with the outputs of all flip-flops at 0. x z J Q
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationVHDL Testbench Design. Textbook chapters 2.19, , 9.5
VHDL Testbench Design Textbook chapters 2.19, 4.10-4.12, 9.5 The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationVHDL: Code Structure. 1
VHDL: Code Structure talarico@gonzaga.edu 1 Mo:va:on for HDL- based design Standard Technology/vendor independent Portable and Reusable talarico@gonzaga.edu 2 Altera s Design Flow (RTL) RTL Generic Boolean
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing asynchronous circuit 4. Inference of basic memory elements
More informationDesign Problem 5 Solution
CSE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solution Jon Turner Due 5/3/05 1. (150 points) In this problem, you are to extend the design of the basic processor to implement
More informationTest Benches - Module 8
Test Benches Module 8 Jim Duckworth, WPI 1 Overview We have concentrated on VHDL for synthesis Can also use VHDL as a test language Very important to conduct comprehensive verification on your design To
More informationComputer-Aided Digital System Design VHDL
بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles
More informationDesign Problem 5 Solutions
CS/EE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solutions Jon Turner Due 5/4/04 1. (100 points) In this problem, you will implement a simple shared memory multiprocessor system
More informationProblem Set 5 Solutions
Problem Set 5 Solutions library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; -- here is the declaration of entity entity la_rewarder is port (clk, go, SRAM_busy, SRAM_rdy: in std_logic; min:
More informationDigital System Construction
Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion
More informationVHDL/Verilog Simulation. Testbench Design
VHDL/Verilog Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus of UUT inputs
More informationCOVER SHEET: Total: Regrade Info: 7 (6 points) 2 (10 points) 9 (5 points) 8 (12 points) 12 (5 points) 11 (25 points)
EEL 4712 Midterm 3 Spring 2012 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
More informationLab 3. Advanced VHDL
Lab 3 Advanced VHDL Lab 3 Advanced VHDL This lab will demonstrate many advanced VHDL techniques and how they can be used to your advantage to create efficient VHDL code. Topics include operator balancing,
More informationEECE 353: Digital Systems Design Lecture 10: Datapath Circuits
EECE 353: Digital Systems Design Lecture 10: Datapath Circuits Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353 Introduction to lecture 10 Large digital systems are more
More informationDepartment of Electronics & Communication Engineering Lab Manual E-CAD Lab
Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated
More informationCDA 4253 FPGA System Design Op7miza7on Techniques. Hao Zheng Comp S ci & Eng Univ of South Florida
CDA 4253 FPGA System Design Op7miza7on Techniques Hao Zheng Comp S ci & Eng Univ of South Florida 1 Extracted from Advanced FPGA Design by Steve Kilts 2 Op7miza7on for Performance 3 Performance Defini7ons
More information