Design Problem 4 Solutions

Size: px
Start display at page:

Download "Design Problem 4 Solutions"

Transcription

1 CSE 260 Digital Computers: Organization and Logical Design Design Problem 4 Solutions Jon Turner The block diagram appears below. The controller includes a state machine with three states (normal, movecursor, regenmaze). The random and vgadisplay blocks at the right are sub-circuits. The random block produces a sequence of pseudo-random bits, one bit of which is stored in pixeltype from time-totime. The vgadisplay block has an internal display memory, which is used by the controller to display the maze. At the bottom left are registers for storing new and old position values. When the cursor moves, the new value is stored in news, newy. After an update is complete, the new position is stored in oldx, oldy. The tick register is used for timing by the controller. The leftpix register stores the color value of the leftmost pixel of the middle row of a 5x5 block. This is read from the vgadisplay s internal memory so that when a cursor is written to the memory, we get the color of the leftmost pixel correct (we need to write all five pixels in a row of a 5x5 block, only two of which are used for the cursor). The linecolor and bgcolor are used to form the data that goes to the display. There are several cases here, but the details are not shown in the diagram

2 The state diagram appears below. It has three states, normal, regenmaze and movecursor. The circuit enters the regenmaze state after reset, in order to create an initial maze. In the regenmaze state, it writes each of the 5x5 blocks that make up the maze, using a random bit value to decide the type of each block (line on left side, or line on top). When it is done generating the maze, it write the cursor in the maze at the position specified by the xpos, ypos inputs. The timing of these operations is controlled by the tick register, which is incremented on every clock tick. The circuit stays in the regenmaze state until after all the steps have been done. This happens when tick reaches some value represented here by xx. When tick reaches this value, the circuit goes to the normal state. In the normal state, the circuit does nothing but wait for an input change. If the numaze input goes high, it transitions to the regenmaze state. If xpos or ypos changes, it goes to the movecursor state. In the movecursor state, the circuit writes the cursor at the appropriate location, using the xpos and ypos values. It first erases the cursor from its old position, then writes the cursor at its new position. When it is finished, the new position becomes the old position

3 Here is the source code for the mazerunner circuit MazeRunner - circuit for displaying a maze and with a cursor around maze -- Jon Turner - 9/ The maze consists of 5x5 pixel blocks organized as an array of 24 rows -- and 32 columns. Each block has a line across the top or along the left -- side A 1 on the numaze signal causes the circuit to generate and display a -- new random maze. The background color of the maze is specified by bgcolor -- and the lines that define the walls of the maze are drawn using linecolor. -- The xpos, ypos inputs specify the x and y position of the cursor in the -- maze; ypos is required to be in the range library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.commondefs.all; entity mazerunner is port( clk, reset: in std_logic; numaze: in std_logic; linecolor, bgcolor: in std_logic_vector(2 downto 0); xpos, ypos: in std_logic_vector(4 downto 0); -- output signals to drive VGA display hsync, vsync: out std_logic; dispval: out std_logic_vector(2 downto 0)); end mazerunner; architecture a1 of mazerunner is component vgadisplay port ( clk, reset: in std_logic; en, rw: in std_logic; addr: in address; data: inout word; hsync, vsync: out std_logic; dispval: out std_logic_vector(2 downto 0)); end component; component random port( clk, reset: in std_logic; randbits: out std_logic_vector(0 to 15)); end component; -- signals used to read/write display buffer signal en, rw: std_logic; signal addr: address; signal data, memword: word; -- state and timer register type statetype is (normal, movecursor, regenmaze); signal state: statetype; - 3 -

4 signal tick: std_logic_vector(15 downto 0); -- old and new positions signal ypos, oldx, oldy, newx, newy: std_logic_vector(4 downto 0); signal randbits: std_logic_vector(0 to 15); signal pixeltype: std_logic; signal leftpix: std_logic_vector(2 downto 0); begin vga: vgadisplay port map(clk, reset, en, rw, addr, data, hsync, vsync, dispval); rand: random port map(clk, reset, randbits); process (clk) begin if rising_edge(clk) then -- default values of several signals en <= '0'; rw <= '1'; addr <= (others => '0'); data <= (others => 'Z'); tick <= (others => '0'); if reset = '1' then state <= regenmaze; oldx <= "00000"; oldy <= "00000"; newx <= "00000"; newy <= "00000"; elsif state = regenmaze then -- redraw maze and place cursor at specified position tick <= tick + 1; if tick(15 downto 12) < "0011" then -- Block to be written is selected using upper bits of tick; -- row number is tick(13..9), col number is tick(8..4) if tick(3 downto 0) = x"0" then pixeltype <= randbits(0); elsif tick(3 downto 0) = x"1" then en <= '1'; rw <= '0'; addr <= ("00" & tick(13 downto 9) & "00000") + (tick(13 downto 9) & " ") + (" " & tick(8 downto 4)); if pixeltype = '0' then data <= "0" & linecolor & linecolor & linecolor & linecolor & linecolor; else data <= "0" & linecolor & bgcolor & bgcolor & bgcolor & bgcolor; elsif tick(3 downto 0) <= x"5" then en <= '1'; rw <= '0'; addr <= addr + x"020"; if pixeltype = '0' then data <= "0" & bgcolor & bgcolor & bgcolor & bgcolor & bgcolor; else data <= "0" & linecolor & bgcolor & bgcolor & bgcolor & bgcolor; else -- finish up by displaying cursor and going to normal state if tick(3 downto 0) = x"0" then - 4 -

5 newx <= xpos; newy <= ypos; oldx <= xpos; oldy <= ypos; elsif tick(3 downto 0) = x"1" then -- first must read color of leftmost pixel in cursor rows en <= '1'; addr <= ("00" & newy & "00000") + (newy & " ") + x"040" + (" " & newx); elsif tick(3 downto 0) = x"3" then leftpix <= data(14 downto 12); elsif tick(3 downto 0) = x"4" then -- now write the first cursor row en <= '1'; rw <= '0'; addr <= ("00" & newy & "00000") + (newy & " ") + x"040" + (" " & newx); data <= "0" & leftpix & bgcolor & linecolor & linecolor & bgcolor; elsif tick(3 downto 0) = x"5" then -- now write the second row en <= '1'; rw <= '0'; addr <= ("00" & newy & "00000") + (newy & " ") + x"060" + (" " & newx); data <= "0" & leftpix & bgcolor & linecolor & linecolor & bgcolor; elsif tick(3 downto 0) = x"6" then state <= normal; elsif state = movecursor then tick <= tick + 1; -- erase the old cursor if tick(3 downto 0) = x"1" then -- first read the color of the left pixel in the cursor rows en <= '1'; addr <= ("00" & oldy & "00000") + (oldy & " ") + x"040" + (" " & oldx); elsif tick(3 downto 0) = x"3" then leftpix <= data(14 downto 12); elsif tick(3 downto 0) = x"4" then -- then write the first cursor row en <= '1'; rw <= '0'; addr <= ("00" & oldy & "00000") + (oldy & " ") + x"040" + (" " & oldx); data <= "0" & leftpix & bgcolor & bgcolor & bgcolor & bgcolor; elsif tick(3 downto 0) = x"5" then -- and the second cursor row en <= '1'; rw <= '0'; addr <= ("00" & oldy & "00000") + (oldy & " ") + x"060" + (" " & oldx); data <= "0" & leftpix & bgcolor & bgcolor & bgcolor & bgcolor; -- now draw the cursor in the new position elsif tick(3 downto 0) = x"6" then en <= '1'; addr <= ("00" & newy & "00000") + (newy & " ") + x"040" + (" " & newx); - 5 -

6 elsif tick(3 downto 0) = x"8" then leftpix <= data(14 downto 12); elsif tick(3 downto 0) = x"9" then en <= '1'; rw <= '0'; addr <= ("00" & newy & "00000") + (newy & " ") + x"040" + (" " & newx); data <= "0" & leftpix & bgcolor & linecolor & linecolor & bgcolor; elsif tick(3 downto 0) = x"a" then en <= '1'; rw <= '0'; addr <= ("00" & newy & "00000") + (newy & " ") + x"060" + (" " & newx); data <= "0" & leftpix & bgcolor & linecolor & linecolor & bgcolor; elsif tick(3 downto 0) = x"b" then -- update old position and go back to normal state oldx <= newx; oldy <= newy; state <= normal; else -- normal state - nothing to do, but switch to other states if numaze = '1' then state <= regenmaze; elsif xpos /= oldx or ypos /= oldy then newx <= xpos; newy <= ypos; state <= movecursor; end process; end a1; - 6 -

7 Here is the source code for displaymod Display Module for mazerunner -- Jon Turner, 10/ This circuit displays the color values used by the mazerunner circuit -- to draw the maze, and the current x and y positions of the cursor. -- The first line of the display provides labels (lc, bc, xp and yp), -- while the second gives the actual values library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commondefs.all; entity displaymod is port( clk, reset : in std_logic; -- internal interface for controlling display linecolor, bgcolor: std_logic_vector(2 downto 0); xpos, ypos: std_logic_vector(4 downto 0); -- connections to external pins lcd: out lcdsigs); end displaymod; architecture a1 of displaymod is component lcddisplay port( clk, reset : in std_logic; -- internal interface for controlling display update: in std_logic; -- update a stored value selekt: in std_logic_vector(4 downto 0); -- character to replace nuchar: in std_logic_vector(7 downto 0); -- new character value -- connections to external pins lcd: out lcdsigs); end component; -- signals for controlling lcddisplay signal update: std_logic; signal selekt: std_logic_vector(4 downto 0); signal nuchar: std_logic_vector(7 downto 0); -- timing signal constant tickwidth : integer := 6+10*operationMode; signal tick: std_logic_vector(tickwidth-1 downto 0); type hex2asciimap is array(0 to 15) of std_logic_vector(7 downto 0); signal hex2ascii: hex2asciimap := ( x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37",x"38",x"39", x"61",x"62",x"63",x"64",x"65",x"66" -- a-f ); begin ldc: lcddisplay port map(clk,reset,update,selekt,nuchar,lcd); process(clk) begin - 7 -

8 if rising_edge(clk) then if reset = '1' then tick <= (others => '0'); else tick <= tick + 1; selekt <= tick(4 downto 0); update <= '0'; if tick(tick high downto 5) = (tick high downto 5=>'0') then update <= '1'; case tick(4 downto 0) is when "00001" => nuchar <= x"6c"; -- l when "00010" => nuchar <= x"63"; -- c end process; end a1; when "00101" => nuchar <= x"62"; -- b when "00110" => nuchar <= x"63"; -- c when "01001" => nuchar <= x"78"; -- x when "01010" => nuchar <= x"70"; -- p when "01101" => nuchar <= x"79"; -- y when "01110" => nuchar <= x"70"; -- p when "10010" => nuchar <= hex2ascii(int("0" & linecolor)); when "10110" => nuchar <= hex2ascii(int("0" & bgcolor)); when "11001" => nuchar <= hex2ascii(int("000" & xpos(4))); when "11010" => nuchar <= hex2ascii(int(xpos(3 downto 0))); when "11101" => nuchar <= hex2ascii(int("000" & ypos(4))); when "11110" => nuchar <= hex2ascii(int(ypos(3 downto 0))); when others => nuchar <= x"20"; end case; - 8 -

9 Here is the source code for the testbench Testbench for mazerunner (top level test) -- Jon Turner - 10/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.commondefs.all; use work.txt_util.all; entity testall is end testall; architecture a1 of testall is component top port( clk: in std_logic; -- buttons and knob, switches and LEDs btn: in buttons; knob: knobsigs; swt: in switches; led: out leds; -- external signals to display lcd: out lcdsigs; -- signals to vga display hsync, vsync: out std_logic; dispval: out std_logic_vector(2 downto 0)); end component; signal clk: std_logic := '0'; signal rot: std_logic_vector(1 downto 0); signal btn: buttons := (others => '0'); signal knob: knobsigs := (others => '0'); signal swt: switches; signal led: leds; signal lcd: lcdsigs; signal hsync, vsync: std_logic; signal dispval: std_logic_vector(2 downto 0); constant clkp : time := 20 ns; constant pause : time := 8*clkP; type testvector is record reset, numaze, load, xysel, colorsel: std_logic; color: std_logic_vector(2 downto 0); turns: integer; -- number of times to turn knob pause: time; end record; type testdata is array(natural range <>) of testvector; constant td: testdata(0 to 20) := ( -- row 1,2 just reset the ciruit -- row 3 turns the knob clockwise 3 times (incrementing xpos) -- row 5 turns the knob clockwise twice while selecting y -- row 7 turns the knob counter-clockwise (decrementing xpos) -- row 9 changes the background color - 9 -

10 ); -- row 11 changes the line color -- row 13 generates a new maze -- row 15 turns the knob clockwise once in the new maze -- reset numaze load xysel colorsel color turns pause 1 => ('1', '0', '0', '0', '0', "000", 0, pause), 2 => ('0', '0', '0', '0', '0', "000", 0, 350 us), 3 => ('0', '0', '0', '0', '0', "000", 3, 2 us), 5 => ('0', '0', '0', '1', '0', "000", 2, 2 us), 7 => ('0', '0', '0', '0', '0', "000", -2, 2 us), 9 => ('0', '0', '1', '0', '0', "110", 0, pause), 11 => ('0', '0', '1', '0', '1', "010", 0, pause), 13 => ('0', '1', '0', '0', '0', "000", 0, 350 us), 15 => ('0', '0', '0', '0', '0', "000", 1, 2 us), others => ('0', '0', '0', '0', '0', "000", 0, pause) begin uut: top port map (clk, btn, knob, swt, led, lcd, hsync, vsync, dispval); process begin -- clock process clk <= '0'; wait for clkp/2; clk <= '1'; wait for clkp/2; end process; knob(2 downto 1) <= rot; knob(0) <= '0'; process begin -- stimulus process rot <= "00"; wait for pause; for i in td'low to td'high loop -- set buttons and switches from test data vector btn <= (0 => td(i).reset, 1 => td(i).numaze, 2 => td(i).load, 3 => td(i).xysel); -- swt <= (3 => td(i).colorsel, (2 downto 0) => td(i).color); swt(3) <= td(i).colorsel; swt(2) <= td(i).color(2); swt(1) <= td(i).color(1); swt(0) <= td(i).color(0); if td(i).turns > 0 then -- turn knob right turns times for i in 1 to td(i).turns loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for pause; end loop; elsif td(i).turns < 0 then -- turn knob left turns times for i in 1 to -td(i).turns loop rot <= "10"; wait for pause; rot <= "11"; wait for pause; rot <= "01"; wait for pause; rot <= "00"; wait for pause; end loop; wait for td(i).pause; end loop; assert (false) report "Simulation ended normally." severity failure; end process; end;

11 The figure below shows an overview of the simulation. More detailed views are on later pages. Note the mazerunner states changing in response to the inputs from the testbench. In this view, you can also see some of the changes to the xpos and ypos values and the changes to the colors. You can also observe the final color values in both the leds and the character buffer of the lcd display. And you can see the final values of xpos and ypos in the lcd character buffer. These observations allow us to conclude that the inputs are properly controlling these internal values and that the lcd display is getting the values it is supposed to display. Of course, the ultimate proof for the lcd can only come with viewing the running circuit on the S3 board

12 This next section shows the very beginning of the simulation, at the start of the maze regeneration following reset. At left, we see the circuit writing data to addresses 0, x020, x040, x060 and x080. At right, we see it writing to data to addresses 001, 021, 041, 061 and 081. These are the addresses for the first two 5x5 blocks in the top row. We can also see that the first word is getting a different value from the other words. This indicates that in both blocks, the line appears on the top. Although we can t see the data values for the first words of each block, we can infer they must be zero and we can see that the other words get the value o77777, which means that all the pixels are white

13 The next section shows the writing of a block for which the line is along the left side of the block, rather than the top. Notice that all lines of the block have 0 in the first pixel (black) and 7 in the remaining four pixels (white)

14 The simulation continues below, with the writing of the cursor at the end of the maze regeneration process. At left, we see the circuit reading from the display buffer (en=1 and rw=1). The address of 040 indicates that we re reading the third line of the first 5x5 block. The returned value is o At right, we see the cursor being written to addresses 040 and 060 (the third and fourth lines of the first 5x5 block). The new data value is o77007, giving us a white square, 2 pixels wide by 2 pixels high

15 This next figure shows a section near the middle of the simulation run (just before the maze is generated a second time). At the left, we can see some changes happening to xpos, as a result of the knob turning. In the middle, we see changes to ypos as the knob turns while xyselect is high. And at right, we see xpos getting smaller as the knob is turned in the other direction. We can see the memory signals in mazerunner changing in response to the changes in xpos and ypos, although we can t see the details at this resolution. Those details can be seen on the next page

16 Here is a view showing the details of the memory signals, as a result of ypos changing from 0 to 1 (near left of figure). Near the middle of the figure, we can see the circuit read the third line from the block containing the cursor. This line has the value o To the right of this, we can see the circuit writing o77777 to the third and fourth lines of that block, effectively erasing the cursor. Continuing to the right, we can see the circuit read the third line from the block where the cursor is to go. This line has the value o07777, indicating that the line is on the left side of the block. At the far right, we see the circuit writing o07007 in the third and fourth lines of the block, effectively drawing a black cursor within the white background

17 This final detail of the simulation shows the writing of the first block of a new maze with new colors. Notice that the line color is now 2 (green) and the background color is 6 (yellow). We see data being written to addresses x00, x20, x40, x60 and x80 (the five words that make up the first block). The value o22222 is written in the first word, giving us a green line across the top of the block, and o66666 is written to the four other words, giving us the yellow background

CSE 260 Digital Computers: Organization and Logical Design. Exam 2. Jon Turner 3/28/2012

CSE 260 Digital Computers: Organization and Logical Design. Exam 2. Jon Turner 3/28/2012 CSE 260 Digital Computers: Organization and Logical Design Exam 2 Jon Turner 3/28/2012 1. (15 points). Draw a diagram for a circuit that implements the VHDL module shown below. Your diagram may include

More information

CSE 260 Digital Computers: Organization and Logical Design. Exam 2 Solutions

CSE 260 Digital Computers: Organization and Logical Design. Exam 2 Solutions CSE 260 Digital Computers: Organization and Logical Design Exam 2 Solutions Jon Turner 1. (10 points). The table at right shows a table with 5 rows and three columns with each column having a heading.

More information

Design Problem 3 Solutions

Design Problem 3 Solutions CSE 260 Digital Computers: Organization and Logical Design Jon Turner Design Problem 3 Solutions In this problem, you are to design, simulate and implement a sequential pattern spotter, using VHDL. This

More information

Design Problem 5 Solutions

Design Problem 5 Solutions CS/EE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solutions Jon Turner Due 5/4/04 1. (100 points) In this problem, you will implement a simple shared memory multiprocessor system

More information

Problem Set 10 Solutions

Problem Set 10 Solutions CSE 260 Digital Computers: Organization and Logical Design Problem Set 10 Solutions Jon Turner thru 6.20 1. The diagram below shows a memory array containing 32 words of 2 bits each. Label each memory

More information

Design Problem 6 Solution

Design Problem 6 Solution CSE 260 Digital Computers: Organization and Logical Design Design Problem 6 Solution Jon Turner The modifications to the VHDL for the console appear below entity console end console; architecture a1 of

More information

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for

More information

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014 CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not

More information

Example 15: Moving Sprites with Flash Background

Example 15: Moving Sprites with Flash Background Displaying an Image Read from Flash Memory 95 Listing 2.5 (cont.) vga_flash_n2_top.vhd clr

More information

CS/EE Homework 7 Solutions

CS/EE Homework 7 Solutions CS/EE 260 - Homework 7 Solutions 4/2/2001 1. (20 points) A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111,

More information

Counters. Counter Types. Variations. Modulo Gray Code BCD (Decimal) Decade Ring Johnson (twisted ring) LFSR

Counters. Counter Types. Variations. Modulo Gray Code BCD (Decimal) Decade Ring Johnson (twisted ring) LFSR CE 1911 Counters Counter Types Modulo Gray Code BC (ecimal) ecade Ring Johnson (twisted ring) LFSR Variations Asynchronous / Synchronous Up/own Loadable 2 tj Modulo-n (n = a power of 2) Asynchronous Count

More information

Sequential Statement

Sequential Statement Sequential Statement Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential

More information

EENG 2910 Project III: Digital System Design. Due: 04/30/2014. Team Members: University of North Texas Department of Electrical Engineering

EENG 2910 Project III: Digital System Design. Due: 04/30/2014. Team Members: University of North Texas Department of Electrical Engineering EENG 2910 Project III: Digital System Design Due: 04/30/2014 Team Members: University of North Texas Department of Electrical Engineering Table of Content i Contents Abstract...3 Introduction...3 Report...4

More information

Example 58: Traffic Lights

Example 58: Traffic Lights 208 Chapter 8 Listing 8.7(cont.) doorlock2_top.vhd btn012

More information

Sequential Logic - Module 5

Sequential Logic - Module 5 Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the

More information

Problem Set 5 Solutions

Problem Set 5 Solutions Problem Set 5 Solutions library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; -- here is the declaration of entity entity la_rewarder is port (clk, go, SRAM_busy, SRAM_rdy: in std_logic; min:

More information

Summary of FPGA & VHDL

Summary of FPGA & VHDL FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:

More information

Test Benches - Module 8

Test Benches - Module 8 Test Benches Module 8 Jim Duckworth, WPI 1 Overview We have concentrated on VHDL for synthesis Can also use VHDL as a test language Very important to conduct comprehensive verification on your design To

More information

Introduction to Computer Design

Introduction to Computer Design Introduction to Computer Design Memory (W 800-840) Basic processor operation Processor organization Executing instructions Processor implementation using VHDL 1 Random Access Memory data_in address read/write

More information

The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #6 Solution

The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #6 Solution 5.3(a)(2), 5.6(c)(2), 5.2(2), 8.2(2), 8.8(2) The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 25 Homework #6 Solution 5.3 (a) For the following SM chart:

More information

COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)

COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points) EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read

More information

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1 Solutions

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1 Solutions CSE 6 Introduction to igital Logic and Computer esign Exam Solutions Jonathan Turner /3/4. ( points) raw a logic diagram that implements the expression (B+C)(C +)(B+ ) directly (do not simplify first),

More information

Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Output Sum(4 bits) Adder. Output carry(1 bit)

Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Output Sum(4 bits) Adder. Output carry(1 bit) Csc 343 Lab 2 Sep 28. 07 Objective: Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Structure: Input A (4 bits) Input B (4 bit) Adder Output Sum(4 bits) Output carry(1 bit) input cin

More information

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs IGITAL LOGIC SIGN VHL Coding for FPGAs SUNTIAL CIRCUITS Unit 5 Asynchronous sequential circuits: Latches Synchronous circuits: flip flops, counters, registers. Testbench: Generating stimulus COMBINATIONAL

More information

VHDL Testbench Design. Textbook chapters 2.19, , 9.5

VHDL Testbench Design. Textbook chapters 2.19, , 9.5 VHDL Testbench Design Textbook chapters 2.19, 4.10-4.12, 9.5 The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus

More information

Lecture 6. Digital Design Laboratory. Copyright 2007, 2009, 2010, 2014 Thomas R. Collins, Kevin Johnson

Lecture 6. Digital Design Laboratory. Copyright 2007, 2009, 2010, 2014 Thomas R. Collins, Kevin Johnson Lecture 6 Digital Design Laboratory Copyright 2007, 2009, 2010, 2014 Thomas R. Collins, Kevin Johnson Recent changes We updated the train simulator, lecture slides, and lab manual in Fall 2014 and again

More information

ECE 545 Lecture 4. Simple Testbenches. George Mason University

ECE 545 Lecture 4. Simple Testbenches. George Mason University ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench

More information

In our case Dr. Johnson is setting the best practices

In our case Dr. Johnson is setting the best practices VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry

More information

Timing in synchronous systems

Timing in synchronous systems BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHL-code that introduces latches andf flip-flops Initialization of registers Mealy- and Moore machines

More information

Codec. WM8731 Audio Codec

Codec. WM8731 Audio Codec Codec WM8731 Audio Codec Codec Coder / Decoder Audio, Video Compression/decompression signal coding 2 tj WM8731 3 tj WM8731 Data Path Basic Connection 4 tj WM8731 Data Path Basic Timing 5 tj WM8731 Data

More information

Sign here to give permission for your test to be returned in class, where others might see your score:

Sign here to give permission for your test to be returned in class, where others might see your score: EEL 4712 Midterm 2 Spring 216 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

VHDL in 1h. Martin Schöberl

VHDL in 1h. Martin Schöberl VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset

More information

VHDL Simulation. Testbench Design

VHDL Simulation. Testbench Design VHDL Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus of UUT inputs algorithmic

More information

Concurrent & Sequential Stmts. (Review)

Concurrent & Sequential Stmts. (Review) VHDL Introduction, Part II Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer Academic Publishers, 2001, ISBN 0-7923-7439-

More information

The University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution Spring 2016

The University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution Spring 2016 The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam Solution Spring 2016 1. (15 points) Write a VHDL function that accepts a std_logic_vector of arbitrary length and an integer

More information

Simulation with ModelSim Altera from Quartus II

Simulation with ModelSim Altera from Quartus II Simulation with ModelSim Altera from Quartus II Quick Start Guide Embedded System Course LAP IC EPFL 2010 Version 0.6 (Preliminary) René Beuchat, Cagri Onal 1 Installation and documentation Main information

More information

[VARIABLE declaration] BEGIN. sequential statements

[VARIABLE declaration] BEGIN. sequential statements PROCESS statement (contains sequential statements) Simple signal assignment statement

More information

Simulation with ModelSim Altera from Quartus II

Simulation with ModelSim Altera from Quartus II Simulation with ModelSim Altera from Quartus II Quick Start Guide Embedded System Course LAP IC EPFL 2010 Version 0.5 (Preliminary) René Beuchat, Cagri Onal 1 Installation and documentation Main information

More information

VHDL/Verilog Simulation. Testbench Design

VHDL/Verilog Simulation. Testbench Design VHDL/Verilog Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus of UUT inputs

More information

COVER SHEET: Total: Regrade Info: 2 (6 points) 3 (8 points) 4 (10 points) 8 (12 points) 6 (6 points) 7 (6 points) 9 (30 points) 10 (4 points)

COVER SHEET: Total: Regrade Info: 2 (6 points) 3 (8 points) 4 (10 points) 8 (12 points) 6 (6 points) 7 (6 points) 9 (30 points) 10 (4 points) EEL 4712 Midterm 2 Spring 2010 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read

More information

Lab 3. Advanced VHDL

Lab 3. Advanced VHDL Lab 3 Advanced VHDL Lab 3 Advanced VHDL This lab will demonstrate many advanced VHDL techniques and how they can be used to your advantage to create efficient VHDL code. Topics include operator balancing,

More information

Design Problem 5 Solution

Design Problem 5 Solution CSE 260 Digital Computers: Organization and Logical Design Design Problem 5 Solution Jon Turner Due 5/3/05 1. (150 points) In this problem, you are to extend the design of the basic processor to implement

More information

Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a

Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November

More information

COVER SHEET: Total: Regrade Info: 5 (14 points) 7 (15 points) Midterm 1 Spring 2012 VERSION 1 UFID:

COVER SHEET: Total: Regrade Info: 5 (14 points) 7 (15 points) Midterm 1 Spring 2012 VERSION 1 UFID: EEL 4712 Midterm 1 Spring 2012 VERSION 1 Name: UFID: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer

More information

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes)

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes) Last (family) name: Answer Key First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Midterm

More information

VHDL And Synthesis Review

VHDL And Synthesis Review VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only

More information

EECE 353: Digital Systems Design Lecture 10: Datapath Circuits

EECE 353: Digital Systems Design Lecture 10: Datapath Circuits EECE 353: Digital Systems Design Lecture 10: Datapath Circuits Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353 Introduction to lecture 10 Large digital systems are more

More information

6.111 Lecture # 8. Topics for Today: (as time permits)

6.111 Lecture # 8. Topics for Today: (as time permits) 6.111 Lecture # 8 Topics for Today: (as time permits) 1. Memories 2. Assembling 'packages' for designs 3. Discussion of design procedure 4. Development of a design example using a finite state machine

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state

More information

The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:

The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below: Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and

More information

ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles

ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended

More information

13/06/56 8 ก ก. 08-Case Study

13/06/56 8 ก ก. 08-Case Study 8 ก ก ก 1 ก 2 1 3 VHDL DIVIDER200Hz use IEEE.std_logic_1164.all; entity DIVIDER200Hz is generic (fin: integer :=25000000; --Input frequency fout: integer :=200); --Output frequency end DIVIDER200Hz; architecture

More information

CS/EE Homework 9 Solutions

CS/EE Homework 9 Solutions CS/EE 260 - Homework 9 Solutions 4/16/2001 1. (20 points) Consider the program on page 1-21 and 1-22 of the lecture notes. Suppose the simple processor is augmented with a direct-mapped instruction cache

More information

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit

More information

Nanosistemų programavimo kalbos 5 paskaita. Sekvencinių schemų projektavimas

Nanosistemų programavimo kalbos 5 paskaita. Sekvencinių schemų projektavimas Nanosistemų programavimo kalbos 5 paskaita Sekvencinių schemų projektavimas Terminai Combinational circuit kombinacinė schema (be atminties elementų) Sequential circuit nuosekli (trigerinė, sekvencinė)

More information

Contents. Chapter 9 Datapaths Page 1 of 28

Contents. Chapter 9 Datapaths Page 1 of 28 Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for

More information

Design Problem 4 Solution

Design Problem 4 Solution CSE 260 Digital Computers: Organization and Logical Design Design Problem 4 Solution Jon Turner Due 4/13/06 1. (125 points). In this problem, you will design a packet FIFO, which is a circuit that temporarily

More information

cla library ieee; use ieee.std_logic_1164.all;

cla library ieee; use ieee.std_logic_1164.all; -- cla entity cla is generic( n_g: integer :=4 -- count of bits ); port( x_p : in std_logic_vector (n_g-1 downto 0); y_p : in std_logic_vector (n_g-1 downto 0); cin_p : in std_logic; cla_p :out std_logic_vector

More information

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1 DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,

More information

Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses

Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single

More information

Programmable Logic. Simple Programmable Logic Devices

Programmable Logic. Simple Programmable Logic Devices Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements

More information

VHDL Testbench VHDL Testbench NO Synthesis Test Vectors Input Vector Output Vector Expected Vector UUT : Unit Under Test Clock Generator Error Report Utility 1 Library : STD Library for Testbench use std.standard.all;

More information

XSV Flash Programming and Virtex Configuration

XSV Flash Programming and Virtex Configuration XSV Flash Programming and Virtex Configuration July 5, 2001 (Version 1.1) Application Note by D. Vanden Bout Summary This application note describes the circuits that let the XC95108 CPLD program the Flash

More information

entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority;

entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority; Примери Приоритетен кодер library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity priority is Port ( a,b,c,d : in STD_LOGIC; encoded : out STD_LOGIC_VECTOR(2 downto 0)); end priority; architecture Behavioral

More information

VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2

VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 VHDL: Modeling RAM and Register Files Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components

More information

Esempio FSM Description : library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity esempiofsm is port ( clk: in STD_LOGIC; p: in STD_LOGIC; reset:

More information

EEE8076. Reconfigurable Hardware Design (coursework) Module Outline. Dr A. Bystrov Dr. E.G. Chester. Autumn

EEE8076. Reconfigurable Hardware Design (coursework) Module Outline. Dr A. Bystrov Dr. E.G. Chester. Autumn EEE8076 Reconfigurable Hardware Design (coursework) Module Outline Dr A. Bystrov Dr. E.G. Chester Autumn 2010 1 2 3 4 5 6 7 8 9 10 11 12 Altera UP2 development board, Flex EPF10K70 FPGA www.altera.com/literature/univ/upds.pdf

More information

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic CPE 626 Lecture 6: VHDL Synthesis Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer Engineering

More information

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine:

More information

Getting Started with VHDL

Getting Started with VHDL Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component Entities can be primitive objects or complex objects Architectures are associated

More information

CprE 583 Reconfigurable Computing

CprE 583 Reconfigurable Computing Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering

More information

Solutions - Homework 4 (Due date: November 9:30 am) Presentation and clarity are very important!

Solutions - Homework 4 (Due date: November 9:30 am) Presentation and clarity are very important! DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Solutions - Homework 4 (Due date: November 6th @ 9:3 am) Presentation and clarity are very important!

More information

The University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution March 2, 2006

The University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution March 2, 2006 The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam Solution March 2, 2006 1. (15 points) A barrel shifter is a shift register in which the data can be shifted either by one

More information

ECE 545 Lecture 7. Advanced Testbenches. Required reading. Simple Testbench. Advanced Testbench. Possible Sources of Expected Outputs

ECE 545 Lecture 7. Advanced Testbenches. Required reading. Simple Testbench. Advanced Testbench. Possible Sources of Expected Outputs ECE 545 Lecture 7 Advanced Testbenches George Mason University Steps of the Design Process 1. Text description 2. Interface 3. Pseudocode 4. Block diagram of the Datapath 5. Interface with the division

More information

COE Design Process Tutorial

COE Design Process Tutorial COE 758 - Design Process Tutorial I. Introduction This tutorial describes a formal design process for the creation of digital systems. The aim of this design process is to provide a systematic approach

More information

HDL. Hardware Description Languages extensively used for:

HDL. Hardware Description Languages extensively used for: HDL Hardware Description Languages extensively used for: Describing (digital) hardware (formal documentation) Simulating it Verifying it Synthesizing it (first step of modern design flow) 2 main options:

More information

Sign here to give permission for your test to be returned in class, where others might see your score:

Sign here to give permission for your test to be returned in class, where others might see your score: EEL 4712 Midterm 2 Spring 215 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

ECE 545 Lecture 7. Advanced Testbenches. George Mason University

ECE 545 Lecture 7. Advanced Testbenches. George Mason University ECE 545 Lecture 7 Advanced Testbenches George Mason University Steps of the Design Process 1. Text description 2. Interface 3. Pseudocode 4. Block diagram of the Datapath 5. Interface with the division

More information

-- Fill in values for each generic. -- Fill in values for each signal. SIGNAL load_start : std_ulogic := '1'; SIGNAL clock : std_ulogic := '0';

-- Fill in values for each generic. -- Fill in values for each signal. SIGNAL load_start : std_ulogic := '1'; SIGNAL clock : std_ulogic := '0'; -- Fill in values for each generic -- Fill in values for each signal SIGNAL load_start : std_ulogic := '1'; SIGNAL clock : std_ulogic := '0'; SIGNAL start : std_ulogic_vector(0 TO 15) := "0000000000000000";

More information

The University of Alabama in Huntsville ECE Department CPE Final Exam Solution Spring 2004

The University of Alabama in Huntsville ECE Department CPE Final Exam Solution Spring 2004 The University of Alabama in Huntsville ECE Department CPE 526 01 Final Exam Solution Spring 2004 1. (15 points) An old Thunderbird car has three left and three right tail lights, which flash in unique

More information

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language

More information

Sign here to give permission to return your test in class, where other students might see your score:

Sign here to give permission to return your test in class, where other students might see your score: EEL 4712 Midterm 1 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission to return your test in class, where other students might see your score: IMPORTANT: Please be neat and write (or draw)

More information

VHDL: A Crash Course

VHDL: A Crash Course VHDL: A Crash Course Dr. Manuel Jiménez With contributions by: Irvin Ortiz Flores Electrical and Computer Engineering Department University of Puerto Rico - Mayaguez Outline Background Program Structure

More information

Assignment. Last time. Last time. ECE 4514 Digital Design II. Back to the big picture. Back to the big picture

Assignment. Last time. Last time. ECE 4514 Digital Design II. Back to the big picture. Back to the big picture Assignment Last time Project 4: Using synthesis tools Synplify Pro and Webpack Due 11/11 ning of class Generics Used to parameterize models E.g., Delay, bit width Configurations Configuration specification

More information

Luleå University of Technology Kurskod SMD152 Datum Skrivtid

Luleå University of Technology Kurskod SMD152 Datum Skrivtid Luleå University of Technology Kurskod SMD152 Datum 2003-10-24 Skrivtid 9.00 13.00 1 Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics

More information

Quartus Counter Example. Last updated 9/6/18

Quartus Counter Example. Last updated 9/6/18 Quartus Counter Example Last updated 9/6/18 Create a logic design from start to a DE10 implementation This example uses best design practices This example is not about creating HDL The HDL code will be

More information

VHDL: Code Structure. 1

VHDL: Code Structure. 1 VHDL: Code Structure talarico@gonzaga.edu 1 Mo:va:on for HDL- based design Standard Technology/vendor independent Portable and Reusable talarico@gonzaga.edu 2 Altera s Design Flow (RTL) RTL Generic Boolean

More information

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial

More information

COE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14

COE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14 COE 405, Term 062 Design & Modeling of Digital Systems HW# 1 Solution Due date: Wednesday, March. 14 Q.1. Consider the 4-bit carry-look-ahead adder (CLA) block shown below: A 3 -A 0 B 3 -B 0 C 3 4-bit

More information

Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN

Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed

More information

EITF35: Introduction to Structured VLSI Design

EITF35: Introduction to Structured VLSI Design EITF35: Introduction to Structured VLSI Design Part 2.2.2: VHDL-3 Liang Liu liang.liu@eit.lth.se 1 Outline Inference of Basic Storage Element Some Design Examples DFF with enable Counter Coding Style:

More information

Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis. 26 October - 20 November, 2009

Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis. 26 October - 20 November, 2009 2065-15 Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis 26 October - 20 November, 2009 FPGA Architectures & VHDL Introduction to Synthesis Nizar Abdallah ACTEL Corp.2061

More information

VHDL- VHDL-3. Vsys. maxplus2. Vsys. d:\uoo. vsystem.ini work

VHDL- VHDL-3. Vsys. maxplus2. Vsys. d:\uoo. vsystem.ini work VHDL- VHDL-3 Vsys TextIO maxplus2 Vsys Vsys d:\uoo mem_tb.vhd mem_tb.vec Vsys d:\uoo vsystem.ini work d:\uoo vsystem.ini [library] std = c:/vsystem/std IEEE = c:/vsystem/ieee SIMPRIM = D:/xilinx/vhdl/src/simprims/work

More information

CDA 4253 FPGA System Design VHDL Testbench Development. Hao Zheng Comp. Sci & Eng USF

CDA 4253 FPGA System Design VHDL Testbench Development. Hao Zheng Comp. Sci & Eng USF CDA 4253 FPGA System Design VHDL Testbench Development Hao Zheng Comp. Sci & Eng USF art-4- > 70% projects spent > 40% time in verification 2 Validation, Verification, and Testing Validation: Does the

More information

EITF35: Introduction to Structured VLSI Design

EITF35: Introduction to Structured VLSI Design EITF35: Introduction to Structured VLSI Design Part 2.2.2: VHDL-3 Liang Liu liang.liu@eit.lth.se 1 Outline Inference of Basic Storage Element Some Design Examples DFF with enable Counter Coding Style:

More information

Lecture 5: State Machines, Arrays, Loops. EE 3610 Digital Systems

Lecture 5: State Machines, Arrays, Loops. EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 5: State Machines, Arrays, Loops BCD to Excess-3 (XS 3 ) Code Converter Example: Fig. 2-53 2 Easier to use one type of code (e.g. XS 3 ) over the other type (e.g. BCD)

More information

Design Examples. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning

Design Examples. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning Design Examples ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning BCD to 7-Segment Display 418_04 2 BCD to 7-Segment Display entity BCD_Seven is port(bcd: in std_logic_vector(3

More information

Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003

Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003 Experiment 0 OR3 Gate ECE 332 Section 000 Dr. Ron Hayne June 8, 2003 On my honor I have neither received nor given aid on this report. Signed: Ronald J. Hayne Part I Description of the Experiment Experiment

More information

MAX 10. Memory Modules

MAX 10. Memory Modules MAX 10 Memory Modules Three types of on-chip memory FF based memory embedded in the LEs Most efficient for very small memories Compiler driven Embedded SRAM block 8K bits + 1024 parity bits (9216b) MAX

More information