RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM. BEHAVIORAL DESCRIPTIONS IN VERILOG HDL (Chapter 7)

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1 RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM BEHAVIORAL DESCRIPTIONS IN VERILOG HDL (Chapter 7)

2 INTRODUCTION Conventional method designers had to design at the gate level entry Today s method only use a complex behavior (using HDL language) which then synthesized into gates Behavioral modeling provides flexibility to a design project Previous chapter have discussed three kinds of behaviors in Verilog: 1. Continuous assignments assign 2. Initial behaviors one shot sequential flow 3. Always behaviors cyclic sequential flow

3 INTRODUCTION The term behavior mean an initial or always behavior The term procedural or behavioral statements statements implementing a declared behavior Example1: module sample (out_a); output out_a; reg out_a; initial out_a = 1; endmodule Initial behavior Procedural assignment

4 VERILOG BEHAVIORS Two kind of behaviors initial and always Behavior may consist of a single or block statement Initial behavior: 1. One shot activity flow and expires after all procedural statements have completed execution 2. Typically use to initialize a simulation and create stimulus waveforms for testbench Always behavior: 1. Cyclic activity flow whereby the procedural statements will be reexecute after the last procedural statement has executed 2. Re-execution process continues indefinitely until the simulation is terminated

5 VERILOG BEHAVIORS Behavior declared within a module followed by single statement or begin. end block statement Block statement a set of procedural statements enclosed in begin. end Block statements can be nested within other blocks and each statement will be executed sequentially A module may contain any number of behaviors but must not be nested

6 VERILOG BEHAVIORS Example2: module sample1 (ina, clk, outa, outb, outc); input ina, clk; output outa, outb, outc; reg outa, outb, outc; Verilog behaviors module sample2 (ina, outa, outb, outc); input ina; output outa, outb, outc; reg outa, outb, outc; (posedge clk) begin outa = ina; outb = outa; outc = outb; end endmodule Block statements initial begin outa = ina; outb = outa; begin outc = outb; end end endmodule Nested block statements

7 VERILOG BEHAVIORS Verilog syntax for initial and always initial_construct ::= initial statement always_construct ::= always statement Statement ::= blocking_assignment; non_blocking_assignment; procedural_assigment; procedural_timing_control_statement; Conditional_statement; Case_statement; loop_statement; wait_statement; Disbale_statement; Event_trigger; Seq_block; Par_block; Task_enable; System_task_enable;

8 BEHAVIORAL STATEMENTS Example3: module clock_gen (clock) parameter half_cycle = 50; parameter max_time = 1000; output clock; reg clock; initial always initial endmodule clock = 0; begin #half_cycle clock = ~clock; end #max_time $finish;

9 PROCEDURAL ASSIGNMENT Procedural assignment: 1. Statement that assigns value to a register variable 2. The output only can get value when a procedural statement executes Three types: 1. Use = operator ~ procedural assignment 2. Use keywords assign, force release ~ procedural continuous assignment 3. Use <= operator ~ non-blocking assignment

10 PROCEDURAL CONTINUOUS ASSIGNMENT (PCA) assign deassign PCA 1. Use the same operator = as a procedural assignment but accompanies with keyword assign 2. Use to model the level-sensitive behavior of combinational logic, transparent latches and asynchronous control of sequential parts 3. Only can be made to register variable and never to a net 4. Note that deassign keyword is optional

11 PROCEDURAL CONTINUOUS ASSIGNMENT (PCA) module mux4_pca (a,b,c,d,sel,y); input a,b,c,d; input [1:0] sel; output y; reg y; (select) if (select ==0) assign y = a; else if (select ==1) assign y = b; else if (select ==2) assign y = c; else if (select ==3) assign y = d; else endmodule

12 PROCEDURAL CONTINUOUS ASSIGNMENT (PCA) force release PCA 1. Capable to apply to nets and register variables 2. The execution of force assignment to a net/register will overrides all other drivers until the release is executed 3. Mostly use with hierarchical de-referencing in testbenches

13 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION Four mechanisms exist to control over the time of execution: 1. Delay control 2. Event control 3. Named events 4. Wait construct

14 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION Delay control operator (#) Suspends the activity flow within a behavior by postponing the execution process Two forms for delay control: 1. Placing the delay control operator (#) and 2. Placing a delay_value to the left of procedural statement Exp: # delay_value

15 PROCEDURAL TIMING CONTROLS module sample_clk (clk1, clk2); output clk1,clk2; reg clk1,clk2; AND SYNCHRONIZATION always begin end endmodule #0 #100 #25 #50 #50; clk1=0; clk2=1; clk1=1; clk2=0; clk2=0; clk1=0;

16 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION Event control operator To synchronize the execution of a procedural statement to a change in the value of either an identifier or an expression Two forms of event control 1. Placed before either an even_identifier or even_expression 2. Followed by a statement (event_expression) statement

17 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION module mux4_pca (a,b,c,d,sel,y); input a,b,c,d; input [1:0] sel; Event control operator output y; reg y; Event_expression (select) if (select ==0) assign y = a; else if (select ==1) assign y = b; else if (select ==2) assign y = c; else if (select ==3) assign y = d; else endmodule statement

18 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION Named events Provides a high level mechanism of communication and synchronization within a modules Also known as abstract event Can be declared only in a module, with keyword event The occurrence of the event is determined using operator ->

19 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION module flop_event (clk,reset,load,data,q1,q2); input clk,reset,data,load; output q1,q2; reg q1,q2; event up_edge; (posedge clk) -> up_edge; (up_edge or reset) begin if (reset) q1 = 0; else q1 = data; end (up_edge or load) begin if (!load) q2 = 0; else q2 = data; end endmodule

20 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION The wait construct Use to suspend (but not terminating) the activity flow until an expression is TRUE If expression evaluates is TRUE, the execution is not suspended or will resume back to normal If expression evaluates is FALSE, the execution is suspended until its fulfill TRUE condition

21 PROCEDURAL TIMING CONTROLS AND SYNCHRONIZATION module wait_sample (a,b,en,y1,y2); input a,b,en; output y1,y2; reg y1,y2; always begin wait (en) y1 = a; #100 y2 = b; #100; end endmodule