ECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design

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1 ECE 4514 Digital Design II Spring 2007

2 Abstraction in Hardware Design Remember from last lecture that HDLs offer a textual description of a netlist. Through abstraction in the HDL, we can capture more than a single transistor or gate at a time. Similar to a function call in C that abstracts a large collection of expressions Similar to a Lego castle that abstracts a large collection of Lego bricks Verilog offers three types of abstraction Structural Dataflow Behavioral These two are related, we call both of them just 'behavioral' for now

3 Structural Modeling Describe a module in terms of components R QB S Q Netlist two modules: NAND_1 and NAND_2 net 1: Rbar to NAND_1, input_1 net 2: Sbar to NAND_2, input_2 net 3: NAND_1, output_1 to NAND_2, input_1 etc..

4 Behavioral Modeling Describe a module in terms of input-output behavior input S, R; output Q, QB; if ( S == 1 ) and (R == 0 ) then Set Q to 1, set QB to 0 else if ( S == 1 ) and (R == 1 ) then Set Q to 1, set QB to 1 else if ( S == 0 ) and (R == 0 ) then *Hold current state* else if ( S == 0 ) and (R == 1 ) then Set Q to 0, set QB to 1

5 Behavioral and Structural are dual mechanisms Rbar Sbar my_flop Q Qbar Structural Description explains what happens to Q and Qbar in terms of a netlist of lower-level components Behavioral Description explains what happens to Q and Qbar in terms of Rbar and Sbar

6 Structural and Behavioral are related A model can be expressed as behavior or structure (of lower-level models) Level 1 Rbar Sbar my_flop Q Qbar Level 2 Rbar Sbar NAND NAND Q Qbar

7 Top-down design my_pc motherboard Start here, rewrite behavior into structure until you reach primitive behavior harddisk controller cpu memory io controller integer unit cache regfile ALU shifter NAND NOR Leaf Cells of Primitive Behavior

8 Bottom-up design my_pc motherboard Equivalent Top-level Behavior harddisk controller cpu memory io controller integer unit cache regfile ALU shifter NAND NOR Start here, compose structure into larger modules until you reach equivalent top-level behavior

9 Bottom-up, Top-down are both useful When re-using modules from one design to the next: bottom-up When developing new modules from scratch: top-down In practice, top-down and bottom-up techniques are combined. In Verilog, a given module can be expressed as structure or else as behavior. There are two flavors of 'behavior' in Verilog Behavioral: similar to a sequential description in C Dataflow: a collection of concurrent expressions

10 Example of a hierarchical model 4-bit counter q0 q1 q2 q3 T-ff T-ff T-ff T-ff q q q q reset Top-level structure contains 4 interconnected T flip-flops

11 T flip-flop, behavior clk T-ff q reset Behavior can be captured in three rules: (1) (2) (3) at each negative clock edge: old_state = new_state any time you see a change on old_state: new_state = not old_state q = old_state any time you see a change on reset: new_state = 0

12 T flip-flop, structure T-ff q reset T-flipflop D D-ff q D-flipflop inverter Thus, we can build a 4-bit counter with inverters and D-flipflops reset

13 D flipflop in Verilog module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; reset or negedge clk) if (reset) q <= 1'b0; else q <= d; endmodule

14 D flipflop in Verilog module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; one output port, three input ports 'reg' means that q is a variable reset or negedge clk) if (reset) means: whenever q <= 1'b0; (condition) is true, proceed. else q <= d; endmodule The '<=' is called a dataflow assignment, in this case the effect is similar to assigning d to q This is a behavioral description in dataflow format

15 T flipflop in Verilog module T_FF(q, clk, reset); output q; input clk, reset; wire d; D_FF dff0(q, d, clk, reset); not n1(d, q); endmodule

16 T flipflop in Verilog module T_FF(q, clk, reset); output q; input clk, reset; wire d; D_FF dff0(q, d, clk, reset); not n1(d, q); endmodule connect corresponding terminals of module module D_FF(q, d, clk, reset);

17 T flipflop in Verilog module T_FF(q, clk, reset); output q; input clk, reset; wire d; one output port, two input ports a wire d has no storage: its value is always determined in terms of other variables D_FF dff0(q, d, clk, reset); not n1(d, q); endmodule 'not' is a primitive in Verilog: the simulator understands what this module does. This is a structural description

18 4-bit counter in Verilog module ripple_carry_counter(q, clk, reset); output [3:0] q; input clk, reset; T_FF tff0(q[0], clk, reset); T_FF tff1(q[1], q[0], reset); T_FF tff2(q[2], q[1], reset); T_FF tff3(q[3], q[2], reset); endmodule

19 4-bit counter in Verilog module ripple_carry_counter(q, clk, reset); output [3:0] q; four output ports, two input ports input clk, reset; T_FF tff0(q[0], clk, reset); T_FF tff1(q[1], q[0], reset); T_FF tff2(q[2], q[1], reset); T_FF tff3(q[3], q[2], reset); endmodule This is a structural description

20 Simulation In order to test the 4-bit counter, we need a clock signal and a reset signal. We also need to monitor the counter's output. These activities can be implemented in a testbench. ripple_carry_counter some behavioral code clk reset q[0:3] clk reset q[0:3]

21 Testbench module stimulus; reg clk; reg reset; wire [3:0] q; ripple_carry_counter(q, clk,reset); initial clk = 1'b0; always #5 clk = ~clk; initial begin reset = 1'b1; #15 reset = 1'b0; #180 reset = 1'b1; #10 reset = 1'b0; #20 $finish; end initial $monitor($time, " Output q = %d", q); endmodule

22 Testbench module stimulus; reg clk; reg reset; wire [3:0] q; ripple_carry_counter(q, clk,reset); initial clk = 1'b0; always #5 clk = ~clk; when simulation starts, clk is low each 5 time units, clk will flip value initial begin reset = 1'b1; #15 reset = 1'b0; #180 reset = 1'b1; #10 reset = 1'b0; #20 $finish; end when simulation starts, reset is high. after 15 time units, reset is low. after 180 time units, reset is high. after 10 time units, reset is low. after 20 time units, stop simulation. initial $monitor($time, " Output q = %d", q); endmodule each time q changes, print its value

23 Modelsim

24 Summary Behavioral and Structural Modeling are two complementary forms for Hardware Description They are linked with top-down (behavior into structure) or bottom-up (structure into behavior) design 4-bit counter as an example of bottom-up design Check design files on Blackboard

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/26 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 4 P-2/26 Chapter 4 Modules and Outline of Chapter 4