Lab # 2. Sequential Statements
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1 The Islamic University of Gaza Faculty of Engineering Department of Computer Engineering ECOM 4111: Digital System Lab Lab # 2 Sequential Statements Eng. Alaa O Shama September, 2015
2 Introduction In this Lab we will introduce using of sequential statements, to understand how data manipulated within process. Sequential statements Sequential VHDL statements allow you to describe the operation, or behavior, of your circuit as a sequence of related events. The use of sequential statements to describe combinational logic implies that our use of the term sequential in VHDL is somewhat different from the term as it is often used to describe digital logic. Specifically, sequential statements written in VHDL do not necessarily represent sequential digital logic circuits. As we will see, it is possible (and quite common) to write sequential VHDL statements, using processes and subprograms, to describe what is essentially combinational logic. In this Lab we will look at examples using these sequential statements. We will also examine the various types of sequential statements available in VHDL. Our primary focus will be on those styles of sequential VHDL that are most appropriate for synthesizable design descriptions and for test benches. Sequential statements are found within processes, functions, and procedures. Sequential statements differ from concurrent statements in that they have order dependency. This order dependency may or may not imply a sequential circuit (one involving memory elements). Sequential Statements Types If statement. Case statement. Loop statement. Wait statement. Return statement. Assertion and report statements. A. If statement: Conditional execution statements B. Case statement: if condition then sequential statements... [elsif condition then sequential statements...] [else sequential statements...] end if; Conditionally select One-of-Many statements to execute based on value of selector expression. There can only be one, unique match. Several choices may be lumped together
3 E.g. when ch1 ch2 ch3 => action to be performed for all 3 alternate choices E.g. when A to B => action to be performed for a range of choices Case expression is when choice => statements [others statements...;] end case; C. Loop statement: Executes a group of statements repeatedly Where [label:] iteration scheme loop {sequential statements} end loop [loop_label]; 1) iteration scheme may be: while condition for identifier in range Identifier is Self-defining and visible only in the Loop Range Specifications examples i in 0 to 7 letter in ( 'A', 'B', 'C') j in 7 downto 0 2) The Following Statements may alter the Loop flow: next - Skip execution of following statements and iterate loop exit - Terminate execution of the loop D. Wait statement: Halts Process Execution wait on signal name; wait until Boolean expression; wait for time expression; wait; E. RETURN: Indicate the value a function returns.
4 Example: (Enc_7Seg) Encoder (using if statement): The Entity for the encoder: The behavioral description of encoder using if statement.
5 7-Segment Register (Using case statement, Null statement): The Entity for the seven segment: The behavioral description of seven segment using case statement. Lab. Exercises L. Exercise: Building a component (Enc_7Seg) from the encoder and the 7-seg., then write a test bench to test the Enc_7Seg component. H. Exercise: 1. Write an entity declaration & a behavioral architecture body for an 8-bit multiplexer. (using case statement). 2. Consider a Binary decoder having the following signals Ain, Bin - select control inputs En - enable input D0, D1, D2, D3 - outputs The inputs Ain and Bin control which output is asserted when input En is high. If En is low, the outputs are always low. The 'd' symbol means 'don'tcare'.
6 Write an entity declaration & a behavioral architecture body for a Binary decoder, then write the test bench for the Binary decoder model, and test it using VHDL simulator.
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