Sequential Statements
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1 Sequential Statements Chapter 5 1
2 Outline 1. VHDL process 2. Sequential signal assignment statement 3. Variable assignment statement 4. If statement 5. Case statement 6. Simple for loop statement Chapter 5 2
3 1. VHDL Process Contains a set of sequential statements to be executed sequentially The whole process is a concurrent statement Can be interpreted as a circuit part enclosed inside of a black box May or may not be able to be mapped to physical hardware Chapter 5 3
4 Two types of process A process with a sensitivity list A process with wait statement Chapter 5 4
5 A process with a sensitivity list Syntax process(sensitivity_list) declarations; begin sequential statement; sequential statement;... end process; Chapter 5 5
6 A process is like a circuit part, which can be active (known activated) inactive (known as suspended). A process is activated when a signal in the sensitivity list changes its value Its statements will be executed sequentially until the end of the process Chapter 5 6
7 E.g, 3-input and circuit signal a,b,c,y: std_logic; process(a,b,c) begin y <= a and b and c; end process; How to interpret this: process(a) begin y <= a and b and c; end process; For a combinational circuit, all input should be included in the sensitivity list Chapter 5 7
8 A process with wait statement Process has no sensitivity list Process continues the execution until a wait statement is reached and then suspended Forms of wait statement: wait on signals; wait until boolean_expression; wait for time_expression; Chapter 5 8
9 E.g, 3-input and circuit process begin y <= a and b and c; wait on a, b, c; end process; A process can has multiple wait statements Process with sensitivity list is preferred for synthesis Chapter 5 9
10 2. Sequential signal assignment Syntax statement signal_name <= value_expression; Syntax is identical to the simple concurrent signal assignment Caution: Inside a process, a signal can be assigned multiple times, but only the last assignment takes effect Chapter 5 10
11 E.g., process(a,b,c,d) begin -- y entry := y y <= a or c; -- y exit := a or c; y <= a and b; -- y exit := a and b; y <= c and d; -- y exit := c and d; end process; -- y <= y exit It is same as process(a,b,c,d) begin y <= c and d; end process; What happens if the 3 statements are concurrent statements? Chapter 5 11
12 3. Varible assignment statement Syntax variable_name := value_expression; Assignment takes effect immediately No time dimension (i.e., no delay) Behave like variables in C Difficult to map to hardware (depending on context) Chapter 5 12
13 E.g., process(a,b,c) variable tmp: std_logic; begin tmp := '0'; tmp := tmp or a; tmp := tmp or b; y <= tmp; end process; Chapter 5 13
14 interpretation: process(a,b,c) variable tmp0, tmp1, tmp2: std_logic; begin tmp0 := '0'; tmp1 := tmp0 or a; tmp2 := tmp1 or b; y <= tmp2; end process; Chapter 5 14
15 What happens if signal is used? process(a,b,c,tmp) begin -- tmp entry := tmp tmp <= '0'; -- tmp exit := 0 ; tmp <= tmp or a; -- tmp exit := tmp entry or a; tmp <= tmp or b; -- tmp exit := tmp entry or b; end process; -- tmp <= tmp exit Same as: process(a,b,c,tmp) begin tmp <= tmp or b; end process; Chapter 5 15
16 4. IF statement Syntax Examples Comparison to conditional signal assignment Incomplete branch and incomplete signal assignment Conceptual Implementation Chapter 5 16
17 Syntax if boolean_expr_1 then sequential_statements; elsif boolean_expr_2 then sequential_statements; elsif boolean_expr_3 then sequential_statements;... else sequential_statements; end if; Chapter 5 17
18 E.g., 4-to-1 mux Chapter 5 18
19 E.g., 2-to-2 2 binary decoder Chapter 5 19
20 E.g., 4-to-2 priority encoder Chapter 5 20
21 Comparison to conditional signal assignment Two statements are the same if there is only one output signal in if statement If statement is more flexible Sequential statements can be used in then, elsif and else branches: Multiple statements Nested if statements Chapter 5 21
22 Chapter 5 22
23 e.g., find the max of a, b, c Chapter 5 23
24 e.g., 2 conditional sig assignment codes Chapter 5 24
25 2 conditional sig assign implementations Chapter 5 25
26 e.g., sharing boolean condition Chapter 5 26
27 Chapter 5 27
28 Incomplete branch and incomplete signal assignment According to VHDL definition: Only the then branch is required; elsif and else branches are optional Signals do not need to be assigned in all branch When a signal is unassigned due to omission, it keeps the previous value (implying memory ) Chapter 5 28
29 Incomplete branch E.g., It implies Chapter 5 29
30 fix Chapter 5 30
31 Incomplete signal assignment E.g., Chapter 5 31
32 Fix #1: Fix #2 Chapter 5 32
33 Conceptual implementation Same as conditional signal assignment statement if the if statement consists of One output signal One sequential signal assignment in each branch Multiple sequential statements can be constructed recursively Chapter 5 33
34 e.g. Chapter 5 34
35 e.g. Chapter 5 35
36 Chapter 5 36
37 5. Case statement Syntax Examples Comparison to selected signal assignment statement Incomplete signal assignment Conceptual Implementation Chapter 5 37
38 Syntax case case_expression is when choice_1 => sequential statements; when choice_2 => sequential statements;... when choice_n => sequential statements; end case; Chapter 5 38
39 E.g., 4-to-1 mux Chapter 5 39
40 E.g., 2-to-2 2 binary decoder Chapter 5 40
41 E.g., 4-to-2 priority encoder Chapter 5 41
42 Comparison to selected signal assignment Two statements are the same if there is only one output signal in case statement Case statement is more flexible Sequential statements can be used in choice branches Chapter 5 42
43 Chapter 5 43
44 Incomplete signal assignment According to VHDL definition: Signals do not need to be assigned in all choice branch When a signal is unassigned, it keeps the previous value (implying memory ) Chapter 5 44
45 Incomplete signal assignment E.g., Chapter 5 45
46 Fix #1: Chapter 5 46
47 Fix #2: Chapter 5 47
48 Conceptual implementation Same as selected signal assignment statement if the case statement consists of One output signal One sequential signal assignment in each branch Multiple sequential statements can be constructed recursively Chapter 5 48
49 e.g. Chapter 5 49
50 Chapter 5 50
51 6. Simple for loop statement Syntax Examples Conceptual Implementation Chapter 5 51
52 VHDL provides a variety of loop constructs Only a restricted form of loop can be synthesized Syntax of simple for loop: for index in loop_range loop sequential statements; end loop; loop_range must be static Index assumes value of loop_range from left to right Chapter 5 52
53 E.g., bit-wide xor Chapter 5 53
54 E.g., reduced-xor Chapter 5 54
55 Conceptual implementation Unroll the loop For loop should be treated as shorthand for repetitive statements E.g., bit-wise xor Chapter 5 55
56 E.g., reduced-xor Chapter 5 56
57 Synthesis of sequential statements Concurrent statements Modeled after hardware Have clear, direct mapping to physical structures Sequential statements Intended to describe behavior Flexible and versatile Can be difficult to be realized in hardware Can be easily abused Chapter 5 57
58 Think hardware Designing hardware is not converting a C program to a VHDL program Chapter 5 58
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