Elektrotechnik und Informationstechnik, Stiftungsprofessur hochparallele VLSI Systeme und Neuromikroelektronik. Oberseminar Informationstechnik

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Esmond Peters
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1 Elektrotechnik und Informationstechnik, Stiftungsprofessur hochparallele VLSI Systeme und Neuromikroelektronik Oberseminar Informationstechnik

2 Reminder: Project Work Project Work ONE system ACCOUNT for ALL lab courses (e.g. Schaltkreis- und Systementwurf, Prozessorentwurf, this seminar) Please REGISTER yourself for EACH LAB COURSE Website (Home) Website (Information, Links, Anmeldung) tu-dresden.de/ing/elektrotechnik/iee/hpsn/studium/materialien Login via IDM (ZIH-Login) required. Typical Login ID: e.g. s Register for `OSM Room: TOE 201 Folie Nr. 2

3 Reminder: Project Work Single-Person projects. One student one project work. Topics Choice of topics presented in the lecture You can also make your own project proposal Structure Self-study your topic Give a presentation to the course: Elaborate the problem and present approaches to the solution. Develop and implement the solution in VHDL, simulate it. Hand in a report. Presentation and Report are evaluated to yield your credits. Folie Nr. 3

4 Project Work Typical Structure of VHDL Work Test Bench Simulation Control Stimulus Digital Control e.g. clock, reset, enable data to be processed Control Parameters e.g. temperature, voltage, simulated real-word input Digital Part e.g. FSM or digital filter Behavioral Model Analog, Mixed-Signal or Physical Digital Interface: Control lines operating real stuff represented by the model. Feedback lines providing digital information on the model state Folie Nr. 4

5 Project Work Typical Structure of VHDL Work Test Bench Simulation Control Stimulus Digital Part e.g. FSM or digital filter Behavioral Model Analog, Mixed-Signal or Physical synchronuous digital logic combinational + sequential synthesizable RTL description abstract simplified model explicitly calculates states of analog and physical quantities Folie Nr. 5

6 Project Work Topics Project Work Digital Controller Mixed Signal Behavioural Model PLL Analog PLL PFD, Divider, Binary Search Loop Filter, Oscillator Digital PLL PID controller Oscillator with temperature and voltage dependencies Digital DLL PID controller Digitally adjustable Delay Line, extenal Delay ADC/DAC SAR ADC SAR register / FSM SC charge redistribution network SD-ADC Decimation filter implementation SD-modulator Class D PA Digital FIR design + implementation analog RLC network Power Step-Down DCDC voltage mode regulation PID controller + digital PWM analog RLC network, simple ADC Step-Down DCDC current mode regulation PID controller + digital PWM analog RLC network, simple ADC Step-Down DCDC discontinuous mode pwm control PID controller + digital PWM analog RLC network, simple ADC DCDC Current Mode / controlled LED supply digital controller, PWM, interface analog RLC network, simple ADC Neuro Polychronuous Spinking Neural Network AER busses and arbiters Neurons, Synapses, Axons Leaky IAF neurons configuration registers, spike decoders Neurons, Synapses Time Division Multiplexed Perceptron Multiplexers, Counters, FSM Current mode MDAC, simple non-linear neuron core Other Brushless DC Motor Sequencer, controller Electro-mechanical motor model Your Own Idea?? Folie Nr. 6

7 Parallel Statements Hierachical Design top_level subsystem building block A another subsystem block D block E block F subblock block B block C block C Folie Nr. 7

8 Parallel Statements Hierarchy corresponds to the Instatiation Parallel Statement Inside the Architecture: RTL Example -- signal declarations go here S <= A B Ci; (A, B) AB <= A B; ; OR3_i : OR3 instantiation (I1 => AB, I2 => AC, I3 => BC, O => Co); RTL; Folie Nr. 8

9 VHDL Hierarchy STRUCTURE FOO FULL_ADDER ( A : std_logic; B : std_logic; Ci: std_logic; S : std_logic; Co: std_logic); FULL_ADDER; FULL_ADDER ( A : std_logic; B : std_logic; Ci: std_logic; S : std_logic; Co: std_logic); FULL_ADDER; subblock ADD_BIT1_i : FULL_ADDER (A => OP_A(1), B => OP_B(1), Ci => CARRY(0), S => RES(1), Co => CARRY(1) ); STRUCTURE; instance of subblock port of is connected to bit 1 of signal in block Folie Nr. 9

10 VHDL Hierarchy: Configurations configuration optionally select particular architectures configuration name STRUCTURE_CFG entity FOO STRUCTURE select architecture for FOO ADD_BIT1_i : FULL_ADDER work.full_adder(net); STRUCTURE_CFG; Folie Nr. 10

11 VHDL Hierarchy: Configurations configuration optionally select particular architectures in architecure of entity STRUCTURE_CFG FOO STRUCTURE instance ADD_BIT1_i : FULL_ADDER work.full_adder(net); STRUCTURE_CFG; is an instance of entity architecture Folie Nr. 11

12 VHDL Hierarchy: Configurations configuration optionally select particular architectures for an entity: select the architecture for an instance: o use particular architecture o use specific configuration o can replace the component with different entity o can map ports, even interchange ports configuration specification also within architecture no config -> default binding, last architecture Folie Nr. 12

13 VHDL Hierarchy: Configurations configuration optionally select particular architectures Very wide range of means to select between choices in the hierarchy Most features not supported by synthesis tools Restrict yourself to one top-level configuration or no configurations at all Folie Nr. 13

14 Arithmetic Binary Arithmetic IEEE 1164 logic is the most prominent enumeration type std_logic std_logic_vector signed, unsigned single-bit digital signals multi-bit digital busses std_logic_vector in numerics Folie Nr. 14

15 Arithmetic Binary Arithmetic IEEE 1164 logic is the most prominent enumeration type std_logic std_logic_vector signed, unsigned single-bit digital signals no numerical interpretation multi-bit digital busses std_logic_vector 2 s complement numericsin numerics IEEE; IEEE.std_logic_1164. ; IEEE.numeric_std. ; BAR FOO BAR Folie Nr. 15

16 Binary Arithmetic IEEE; IEEE.std_logic_1164. ; IEEE.numeric_std. ; library and use statements BAR FOO BAR std_logic_vector 0) unsigned(15 0) signed(15 0) U <= unsigned(l); S <= signed(l); L <= U X= 1 S; assignment to subtype with cast direct assignment to base type U <= to_unsigned( 173, 16); S <= to_signed( -212, 16); X <= A( to_integer(u(3 downto 0))); conversion functions Folie Nr. 16

17 Parallel Statements back to Parallel Statements Inside Architectures RTL Example -- signal declarations go here S <= A B Ci; (A, B) AB <= A B; ; process statement OR3_i : OR3 (I1 => AB, I2 => AC, I3 => BC, O => Co); RTL; Folie Nr. 17

18 Process Statement Process Statement A, B, C) A 010 S1 <= B; S1 <= C; ; ; label: ( A) S2 <= A(1) label; A(0); sensitivity list inside the process: sequential statements all processes run in parallel a process can be named with a label Folie Nr. 18

19 Sequential Statements Sequential Statement: if-then-else expression yielding a Boolean value condition sequential_statements; condition sequential_statements; sequential_statements; optional ELSIF branch. optional ELSE branch. required END IF; Folie Nr. 19

20 Sequential Statements Sequential Statement: case expression of arbitrary type expression choice choice choice equential_statements; equential_statements; equential_statements; choice value of same type as expression Folie Nr. 20

21 Sequential Statements Sequential Statement: case As of the VHDL standard, all possible choices must be included, SEL "01" Z A "10" Z B Z 'X' unless the others clause is used as the last choice Folie Nr. 21

22 Sequential Statements Sequential Statement: case SEL "01" Z A "10" Z B null statement explicitly do nothing in this branch Folie Nr. 22

23 Sequential Statements Sequential Statement: case range INT 0 Z A 1 to 3 Z B Z A selection: List of values Folie Nr. 23

24 Sequential Statements Not allowed in case statement: ranges and selections must not overlap INT Z B 4 6 Z A others Z X ranges are not allowed for vectors / arrays VEC 000 Z A Z B others Z X Folie Nr. 24

25 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements Sequential Statement: for loop Loop Variable variable implicitly takes type declared of loop range with type of loop range Z "0000"; I 0 3 A I Z(I) '1' Example for combinational 1-hot decoder Folie Nr. 25

26 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements Sequential Statement: for loop Z "0000"; I 0 3 A I Z(I) 1 End the loop with exit Folie Nr. 26

27 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements Sequential Statement: for loop Skip to next loop iteration with Z "0000"; I 0 3 when A Z(I) 1 and I also work with labels Folie Nr. 27

28 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements for loop example: determine highest bit std_logic_vector(n-1 0 unsigned(k A default assignment M to_unsigned( 0, K) I A LOW A HIGH A(I) 1 M to_unsigned( I, K) Attributes as loop bounds last sequential assignment wins Folie Nr. 28

29 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements another for loop example: determine highest bit std_logic_vector(n-1 0 unsigned(k A Look for highest bit first M to_unsigned( 0, K) I A HIGH A LOW A(I) 1 M to_unsigned( I, K) End the loop if bit is found. Folie Nr. 29

30 Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop; Sequential Statements Variable example: count 1 bits std_logic_vector(n-1 0 unsigned(k A variables explicit intermediate values in processes unsigned(k tmp to_unsigned( 0, K) I A LOW A HIGH A(I) 1 tmp tmp + 1 variable assignment takes effect immediately M <= tmp; Folie Nr. 30

31 Sequential Statements Sequential Statement: wait wait for a fixed time 10 ns; A, B; clk = '1' clk'event clk = '1'; clk'stable clk = '1'; wait for either signal to change wait for a condition to become true A B='1'; combinations allowed Folie Nr. 31

32 Digital Logic = Synthesizable RTL code Test Bench Simulation Control Stimulus Digital Part e.g. FSM or digital filter Behavioral Model Analog, Mixed-Signal or Physical Folie Nr. 32

33 Synthesizable RTL Code Digital logic is subdivided in two principal classes: 1) Combinational Logic 2) Sequential Logic A B D Q clk Computing Elements Storage Elements Folie Nr. 33

34 Synthesizable RTL Code Digital logic is subdivided in two principal classes: 1) Combinational Logic 2) Sequential Logic A B D Q clk Computing Elements Storage Elements Nothing else. Nothing in between. Of course, elements from both classes can be assembled together to form entities with storage and computing capabilities Folie Nr. 34

35 Synthesizable RTL Code 1) Combinational Logic some inputs, some ouputs each change of logic level at any input immediatly followed by change at some output in the physical world delayed by path delay A B C D E Folie Nr. 35

36 Synthesizable RTL Code 1) RTL for Combinational Logic std_logic A B C D E 1 E <= B; E <= C; ; ; 1 std_logic Folie Nr. 36

37 Synthesizable RTL Code 1) RTL for Combinational Logic std_logic A B C D E 1 E <= B; E <= C; ; ; ALL right-hand side signals MUST be in the sensitivity list 1 std_logic Any signal, that gets a value assigned, is said to be an output of the process. A combinational process MUST ASSIGN values to ALL its OUTPUT SIGNALS under any condition Folie Nr. 37

38 Synthesizable RTL Code 1) RTL for Combinational Logic std_logic A B C D E alternatively: 1 E <= B; E <= C; ; ; 1 std_logic concurrent assignments Folie Nr. 38

39 Synthesizable RTL Code 1) RTL for Combinational Logic std_logic A B C D E 1 E <= B; E <= C; ; ; 1 std_logic no delay in RTL Folie Nr. 39

40 Synthesizable RTL Code Operators for Digital Logic / RTL code bit-wise logic and Boolean logic, result type = argument type and, or, nand, nor, xor, xnor, not comparisons, result type: Boolean = /= < > <= / >= equal not equal less than greater than less/greater or equal numeric, result type: numeric +, - addition, subtraction, unary sign O.K. *, / multiplication, division mod,rem modulo division, sign of right (mod) or left (rem) operand ** exponentiation abs absolute value need 3rd party IP Folie Nr. 40

41 Synthesizable RTL Code 2) Sequential Logic clock signal and significant clock edge (e.g. rising_edge(clk)) input data is captured at the time of the clock edge and presented at the output until different data will have been captured at a subsequent clock edge D clk Q Folie Nr. 41

42 Process Statement Process Statement for Sequential Logic EXACTLY clock and reset in the sensitivity list clk, reset_n) reset_n 0 Q <= 0 ; Q <= D; ; ; clk Exacty one top-level ifthen-else clause. Active reset state in the highest-priority branch Active clock edge in the second branch. Folie Nr. 42

43 Synthesizable RTL Code 2) RTL for Sequential Logic D Q clk, reset_n) clk reset_n 0 Q <= 0 ; Q <= D; ; ; clk no delay in RTL Folie Nr. 43

44 Example: Incrementer INC clk std_logic reset_n std_logic Q unsigned(3 0 INC 4 4 RTL INC D : unsigned(3 0 clk, reset_n) reset_n 0 Q <= (others => 0 ); clk Q <= D; ; ; 0001 reset_n 4 +D clk Q D <= Q + to_unsigned( 1, 4); RTL; Folie Nr. 44

Example: Incrementer INC clk std_logic reset_n std_logic Q unsigned(3 0 INC 04.11.

45 Example: Incrementer INC clk std_logic reset_n std_logic Q unsigned(3 0 INC RTL INC D : unsigned(3 0 clk, reset_n) reset_n 0 Q <= (others => 0 ); clk Q <= D; ; ; D <= Q + to_unsigned( 1, 4); RTL; numeric constants decimal, integer real, 4 decimal 16#FF# -- integer, base 16 (i.e. hexadecimal) 2#0001# -- integer, base 2 (i.e. binary) D clk better readability: 16#1A_DEAD_BEEF# -- integer, hex reset_n 1_000_ Folie Nr. 45 Q

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware