Digital Systems Design

Transcription

1 IAY 0600 Example: HalfAdder Behavior Structure Digital Systems Design a b Sum Carry a b HalfAdder Sum Carry VHDL discussion Dataflow Style Combinational Design a Sum Sum = a&b a& b = a b b & Carry Carry = a & b Tallinn University of Technology 2 Example: HalfAdder Behavioral Description Combinational systems a b Sum Sum = a&b a& b = a b HalfAdder Carry Carry = a & b entity HALFADDER is port(a, b: in bit; Sum, Carry: out BIT); end HALFADDER; architecture RTL of HALFADDER is Sum <= a xor b; Carry <= a and b; end RTL; This is data flow behavioral description Combinational systems have no memory. A combinational system's outputs are a function of only its present input values. No latches/ffs or closed feedback loop Combinational system description can be in dataflow, behavioral, or structioral styles. Concurrent signal assignment signal is basic for dataflow style combinational design. We consider three kinds of concurrent signal assignment: Concurrent signal assignment statement using a Boolean expression Selected signal assignment statement Conditional signal assignment statement 3 4 Signal assignment in combinational design Simplified syntax for entity declaration Syntax for synthesizable signal assignment statement Signal assignment statement with a closed feedback loop: a signal appears in both sides of a concurrent assignment statement For example, q <= ((not q) and (not en)) or (d and en); Syntactically correct Form a closed feedback loop Should be avoided 5 Syntax refers to the patern or structure of the word order in a prase. Definitions are simplified for instructional purposes. 6

2 Notation used in syntax definitions 4-to-1 multiplexer using a Bool. expression library ieee; use ieee.std_logic_1164.all entity mux4to1 is port (c3, c2, c1, co: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture dataflow of mux4to1 is y <= not g_bar and ( (not b and a and c0) or (not b and a and c1) or (b and not a and c2) or (b and a and c3)); end dataflow; What is STD_LOGIC you ask? 7 8 STD_LOGIC type BIT versus STD_LOGIC Value Meaning 'U' Uninitialized X Forcing (Strong driven) Unknown 0 Forcing (Strong driven) 0 1 Forcing (Strong driven) 1 Z High Impedance W Weak (Weakly driven) Unknown L Weak (Weakly driven) 0. Models a pull down. H Weak (Weakly driven) 1. Models a pull up. - Don't Care 9 BIT type can only have a value of 0 or 1 STD_LOGIC can have nine values 'U', 0, 1, X, Z, W, L, H, - Useful mainly for simulation 0, 1, and Z are synthesizable 10 Selected signal assignment statement Selected signal assignment statement (ex.) Simplified syntax: with select_expression select signal_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3,... value_expr_n when choice_n; The value of one and only one choice must equal the value of the select expression. library ieee; use ieee.std_logic_1164.all entity mux4to1 is port (c3, c2, c1, c0: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture selected of mux4to1 is with std_logic_vector' (g_bar, b, a) select y <= c0 when "000", c1 when "001", c2 when "010", c3 when "011" '0' when others; -- default end selected; Here we use an aggregate (g_bar, b, a) in a select expression 11 12

3 Type qualification. Choices completeness We must explicitly specify the aggregat's (g_bar, b, a) type. This is accomplished using a type qualification ('): std_logic_vector' (g_bar, b, a) To describe combinational logic, the choices listed in a selected signal assignment must be all inclusive. That is, they must include every possible value of the select expression. y <= c0 when "000", c1 when "001", c2 when "010", c3 when "011" '0' when others; The last clause (default assignment) uses the keyword others to assign the value of 0 to y for the 725 values of the select expression not explicitly listed. 9**3=729, 729-4= Conditional signal assignment statement The result from evaluating a condition is type boolean. type boolean is (false, true) ; The leftmost literal in an enumeration listing is in position 0. Each enumeration type definition defines an ascending range of position numbers. Example: type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') ; ' Z ' (with position number 4) iz greater than ' 1 ' (with position number 3 14 Conditional signal assignment statement Avoiding implied latches library ieee ; use ieee.std_logic_1164.all ; entity mux4to1 is port (c3, c2, c1, co: in std_logic; g_bar, b, a: in std_logic; y: out std_logic); end mux4to1; architecture conditional of mux4to1 is signal tmp : std_logic_vector (2 downto o); tmp <= (g_bar, b, a); y <= c0 when tmp = "000" else c1 when tmp = "001" else c2 when tmp = "010" else c3 when tmp = "011" else '0' ; -- default assignment end conditional; 15 The last value_expression must not have an associated when condition clause (default assignment). For example, let s take previous description. If the conditional signal is written as: y <= c0 when tmp = "000" else c1 when tmp = "001" else c2 when tmp = "010" else c3 when tmp = "011" ; the VHDL interpretation of this construct is that, for the 4 specified values of tmp, a new value should be assigned to y. This implies that for all other values of tmp the y should retain its previous value. As a result, the synthesizer generates a latch at the output of the combinational logic to store the value of y. 16 Synthesised mux logic with undesired latch Behavioral Style Combinational Design (non-)synthesizing Loops (paryty detector example) 17 Tallinn University of Technology

4 Behavioral style features A behavioral style architecture uses algorithms in the form of sequential programs. These sequential programs are called processes. The statement part of a behavioral style architecture consists of one or more processes. Each process statement is, in its entirety, a concurrent statement. Process communicate with each other, and with other concurrent statements, using signals. Statements inside a process are sequential statements. They are executed in sequence and their order is critical to their effect. Sequential control statements select between alternative statement execution paths. 19 Dataflow style half-adder description library ieee; use ieee.std_logic_1164. all; entity half_adder is port (a, b : in std_logic; sum, carry_out : out std_logic); end half_adder; architecture data_flow of half_adder is sum <= a xor b ; carry_out <= a and b ; end data_flow; -- concurrent signal assignment -- concurrent signal assignment Signal assignment statement placed in the statement part of an architecture is a concurrent statement. 20 Behavioral style half-adder description Process statement entity half_adder is port (a, b : in std_logic; sum, carry: out std_logic); end half_adder; architecture behavior of half_adder is ha: process (a, b) if a = 1 then sum <= not b ; carry <= b ; --sequential signal assignments else sum <= b ; carry <= 0 ; end if; end process ha ; end behavior ; 21 A process statement is a concurrent statement that itself is comprised of sequential statements. No signals can be declared in a process. A process with a sensitivity list must not contain any wait statements. A process without a sensitivity list must contain at least one wait statement, or its simulation will never end. A process can be viewed as an infinite loop whose execution is repeatedly suspended and resumed. 22 Process st-ment and combinational logic Process communication Processes statements can be used to describe combinational or sequential systems. Two requirements for a process to synthesize to a combinational system are: The process s sensitivity list must contain all signals read in the process. A signal or variable assigned a value in a process must be assigned a value in all possible executions of the process. 23 In this example, three processes are communicating, using signals (s1, s2, s3), to implement a full adder. Process communication using signals is similar to the way components in a structural description communicate (are connected). 24

5 Full adder representation library ieee; use ieee.std_logic_1164. all; entity full_adder is port (a, b, carry_in : in std_logic; sum, carry_out : out std_logic); end full_adder; architecture processes of full_adder is signal s1, s2, s3 : std_logic; -- Signals to interconnect -- Each process is a concurrent statement ha1: process (a, b) -- ha1 process if a = ' 1 ' then s1 <= not b ; s2 <= b ; else s1 <= b ; s2 <= 0 ; end if; end process ha1; 25 Full adder representation (cont.) ha2: process (s1, carry_in) -- ha2 process if s1 = ' 1 ' then sum <= not carry_in ; s3 <= carry_in ; else sum <= carry_in ; s3 <= ' 0 ' ; end if; end process ha2 ; or1: process (s3, s2) -- or1 process if ( s3 = ' 1 ' ) or ( s2 = ' 1 ' ) then carry_out = ' 1 ' ; else carry_out = ' 0 ' ; end if; end process or1 ; end processes 26 Dataflow description of parity detector PARYTY DETECTOR EXAMPLE (NON-)SYNTHESIZING LOOPS Output oddp is asserted when the number of 1s in the input vector is odd, otherwise it is unasserted. library ieee; use ieee.std_logic_1164. all ; entity parity is port (din : in std_logic_vector (3 downto 0) ; oddp : out std_logic -- aserted for odd parity) ; end parity ; architecture dataflow of parity is oddp <= din (3) xor din (2) xor din (1) xor din (0) ; end dataflow ; Simulation of dataflow style parity detrector Behavioral parity detector (failed)description The testbench sequences through all possible binary input combinations. Input vector din is diplayed as both a composite signal, whose value is expressed in hexadecimal, and in terms of its separate elements. 29 Architecture for parity detector written using a loop and a signal: architecture bihav_sig of parity is signal odd : std_logic ; po : pocess (din) odd <= ' 0 ' ; for index in 3 downto 0 loop odd <= odd xor din (index) ; end loop ; end process ; oddp <= odd ; end behav_sig ; 30

6 Simulation of parity detector Waveforms from simulation of parity detector written using a loop and a signal. How a RTL synthesizer synthesizes a loop The synthesizer unrolls the loop to create the sequence of statements that corresponds to the complete execution of the loop. One copy of the sequence of statements inside the loop is created for each loop iteration. In each copy, the loop parameter is replaced by its value for that loop iteration. The loop is replaced by the statements created by unrolling the loop (behavior is not changing). The simulation resulted in oddp always having the value U. Why??? 31 odd <= '0' ; for index in 3 downto 0 loop odd <= odd xor din (index) ; end loop ; odd <= '0' ; odd <= odd xor din (3) ; odd <= odd xor din (2) ; odd <= odd xor din (1) ; odd <= odd xor din (0) ; 32 How a RTL synthesizer synthesizes a loop Since odd is a signal, the assignment of a value to it does not take affect until the process suspends. As a result, only the last assignment to odd before the process suspends is meaningful. Explanation of simulation result From last assignment statement < odd <= odd xor din (0); > it is clear why the simulation resulted in oddp always having the value U. odd <= odd xor din (0) ; Accordingly, the synthesizer synthesizes next logic: At initialization, odd is given the value U. After the process suspends odd is assigned U xor din (0), which evaluates to U (look the next slide). Thus the process always computes the value U for odd (that is assigned than to oddp) XOR function in STD logic -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( U X 0 1 Z W L H ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- U ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- X ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- 0 ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- 1 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- Z ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- W ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- L ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- H ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- - ); Solution of the problem We need each assignment to odd to take immediately. Thus, we need to use variable to store the value of odd. Look the next slide: the design description is modified by replacing the signal declaration for in the declarative part of the architecture body with a variable declaration for odd in the declarative part of the process. The Sequence of sequential assignments made to variable odd: odd := ' 0 ' ; odd := odd xor din (3) ; odd.= odd xor din (2) ; odd := odd xor din (1) ; odd := odd xor din (0) ; 35 Since assignments take effect immediately, the algorithm work as desired 36

7 Using variables Architecture for parity detctor written using a loop and variable: architecture bihav_var of parity is po : pocess (din) variable odd : std_logic; -- declare a variable default value odd := ' 0 ' ; for index in 3 downto 0 loop odd := odd xor din (index) ; end loop ; oddp <= odd ; end process ; end behav_var ; Synthesis of processes Logic resulting from synthesis using the architecture written with a loop and variable odd := ' 0 ' ; odd := xor din (3) ; odd.= xor din (2) ; odd := xor din (1) ; odd := xor din (0) ; Loops that cannot be synthesized To synthesize a loop, a RTL synthesizer must unroll the loop. This requires that the number of loop iterations be known during synthesis. Thus a for loop with constant bounds can be synthesized. If a variable were used in specifying the loops range bounds (nonconstant bounds), the synthesizer could not statically determine the number of loop iterations. Also a synthesizer cannot statically determine the number of loop iterations of a while loop, since completion of a while loop is dependent on data generated during the loop s execution. 39 Avoiding latches To ensure that the logic synthesized from a process is combinational, all signals and vatiables assigned a value in the process must be assigned a value each time the process executes. If this requirement is not met, latches may be inferred. To insure this requirement is met it might be helpful to assign a default value at the ning of the process to each signal or variable that is assigned values later in the process. 40