Lecture 5: State Machines, Arrays, Loops. EE 3610 Digital Systems
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1 EE 3610: Digital Systems 1 Lecture 5: State Machines, Arrays, Loops
2 BCD to Excess-3 (XS 3 ) Code Converter Example: Fig Easier to use one type of code (e.g. XS 3 ) over the other type (e.g. BCD) in different digital systems We will need a converter
3 What are BCD Codes? 3 Binary Coded Decimal (BCD) Decimal BCD Code DCBA
4 Example: BCD Codes in 7-segment Display [1/2] Binary Coded Decimal (BCD) 4
5 Example: BCD Codes in 7-segment Display [2/2] 7 Segment Display 5
6 Example: BCD Code Usage in Clocks, etc. Clocks, DC Voltmeters 6
7 What are Excess-3 (XS 3 ) Codes? 7 Used to simplify arithmetic operations Can add two decimal numbers Way to represent decimal digits, and each value equals the decimal digit value plus 3 Used in older computers, cash registers, calculators Ref:
8 Excess-3 (XS 3 )Code 1) Add 3 to a given decimal > convert to binary 2) Decimals are 9's complement numbers, Binarys are 1's complement numbers 9's Complement Decimal BCD Code DCBA Excess-3 Binary Code 's Complement (inverted bits)
9 State Machine for BCD to Excess-3 Code Converter 9
10 VHDL for the State Machine 10 Can assign States as positive integers
11 VHDL for the State Machine 11 Default state for any other condition than the ones listed before
12 BCD to XS3 Code Generator: Simulation 12
13 State Machines 13 Rather than assigning state codes, let VHDL Compiler do it Enumerated Types type state_type is(state A, state B,...); signal present_state, next_state:state_type; Now we can write, present_state <= state A;
14 Modeling Next State Register 14 Inputs Next Stage Decoder State Register Output Decoder Outputs Next State process (clk, rst) begin if rst='1' then present_state <= state A; elsif rising_edge(clk) then present_state <= next_state; end if; end process Present State reset State goes here
15 Combine State Machine and Output Decoder process(present_state,...other inputs...) begin case present_state is when state_a => -- assign every output & next_state when state_b => -- assign every output & next_state... end case; end process MAKE SURE to cover every single case, otherwise latches will be created 15
16 Combine State Machine and Output Decoder 16 1) Not necessary: since all outputs and next states of all possible values of present state are explicitly specified. 2) Include it whenever matching else is not included with if statement or when all possible values of states are not specified.
17 How to avoid Latches Make sure that default values are assigned for all outputs process(present_state,...other inputs...) begin out1 <= '0'; out2 <= '1'; ---default case present_state is when state_a => out1 <='1'; next_state <= state_b;... end case; end process In VHDL, it is ok to assign a signal twice in a process. Assign default values and change them only when necessary 17
18 MUX: Using when and else Concurrently 18 F <= I0 when A='0' else I1; F <= I0 when B='00' else I1 when B='01' else I2 when B='10' else I3 when B='11'; bit_array (1 down to 0) not necessary
19 Arrays All arrays must have a new "type" explicitly defined type register_file is array (0 to 255) of std_logic_vector (15 downto 0); signal reg0: register_file Access each element using parentheses reg0(1)<=reg0(2);--cycle Type can be unconstrained (unknown dimension): 19 1) low and high bound are defined when a signal/variable is declared 2) index must be an integral type: natural, positive type intvec is array(natural range <>) of integer; signal intvec5: intvec(1 to 5) := (3,26,8,90,1);
20 Matrices 20 type matrix is array(natural range <>,natural range <>) of integer; signal X: matrix (1 to 6,1 to 10); Access each element using parentheses X(1,2)<= X(3,2);--shuffle
21 Example: Matrix in Parity Code Generator Assign Parity Bits for error detection and correction: Cyclic Redundancy Check (CRC) 21 Method: 1) Count number of 1s 2) Even Parity: Odd number of 1s, Parity bit=1 Even number of 1s, Parity bit=0 3) Odd Parity: Odd number of 1s, Parity bit=0 Even number of 1s, Parity bit=1
22 Example: Odd Parity Code Generator 22 Total number of rows=16 Note that the row number corresponds to the Input bits (address)
23 Example: Parity Code Generator 23 library IEEE; use IEEE.numeric_bit.all; entity parity_gen is port(x: in unsigned(3 downto 0); Y: out unsigned(4 downto 0)); end parity_gen; architecture Table of parity_gen is type OutTable is array(0 to 15) of bit; signal ParityBit: bit; constant T: OutTable := ('1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1'); begin ParityBit <= T(to_integer(X)); Y <= X & ParityBit; end Table; 4 bits 5 bits including the parity bit Use to_integer function to convert unsigned vector to an integer
24 Sequential statements Loops Sometime synthesizable sometimes not For loop (will synthesize and create multiple copies) 24 loop_label: for loop_index in range loop sequential statements; end loop loop_label; While loop (used for simulation only) loop_label: while condition loop sequential statements; end loop loop_label; Sequential Execution
25 4 bit Ripple Carry Adder
26 Loops: Examples 4-bit Ripple Carry Adder with For loop architecture Behavioral of Fourbit_RCAdder is begin --Run for loop with Full Adder equations process(a,b,ci)--sensitivity list variable sum: std_logic_vector(3 downto 0):="0000"; variable Cin,Cout: std_logic:= '0'; begin Cin:=Ci;--Initial Carry_in for i in 0 to 3 loop Run it 4 times since 4-bit sum(i):= A(i) xor B(i) xor Cin; Cout := (A(i) and Cin) or (B(i) and Cin) or (A(i) and B(i)); Cin:=Cout; --Cin for next is Cout end loop; Co <= Cout; S <= sum; end process; end Behavioral; 26
27 Used in test bench Assert, Report, Severity 27
28 Assert, Report, Severity 28
29 Assert, Report, Severity 29 Check the answer to see if it's correct
30 Severity Levels assert <condition>; assert <condition> severity <severitylevel>; assert <condition> report <message_string>; assert <condition> report <message_string>... severity <severitylevel>; 30 Predefined severity names are... NOTE: WARNING: ERROR: (Stops the simulation) FAILURE: (Stops the simulation)
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