Today. Designing with Verilog. Top-Down vs. Bottom-Up (1) Top-Down vs. Bottom-Up (2)
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1 Today Designing with Verilog EECS150 Spring 2006 Lab Lecture #2 Brian Gawalt Greg Gibeling Top-Down and Bottom-Up Partitioning & Interfaces vs. Verilog Administrative Info Blocking and Non-Blocking Verilog and Hardware Lab #2 Primitives 1/27/06 EECS150 Lab Lecture #2 1 1/27/06 EECS150 Lab Lecture #2 2 Top-Down vs. Bottom-Up (1) Top-Down Design Start by defining the project Then break it down Starts here: Top-Down vs. Bottom-Up (2) Top-Down Design Ends here: 1/27/06 EECS150 Lab Lecture #2 3 1/27/06 EECS150 Lab Lecture #2 4 1
2 Top-Down vs. Bottom-Up (3) Bottom-Up Testing Faster, Easier and Cheaper Test each little component thoroughly Allows you to easily replicate working components Partitioning & Interfaces (1) Partitioning Break the large module up Decide what sub-modules make sense Partitioning is for your benefit It needs to make sense to you Each module should be: A reasonable size Indepently testable Successful partitioning allows easier collaboration on a large project 1/27/06 EECS150 Lab Lecture #2 5 1/27/06 EECS150 Lab Lecture #2 6 Partitioning & Interfaces (2) Interfaces A concise definition of signals and timing Timing is vital, do NOT omit it Must be clean Don t s useless signals across Bad partitioning might hinder this An interface is a contract Lets other people use/reuse your module vs. (1) Rule of thumb: doesn t have sub-components has sub-components: Instantiated Modules Instantiated Gates Instantiated Primitives Most modules are mixed Obviously this is the most flexible 1/27/06 EECS150 Lab Lecture #2 7 1/27/06 EECS150 Lab Lecture #2 8 2
3 vs. (2) vs. (3) Lab3Top PeakDetector Accumulator Reg8 Comp8 FDCE Primitive Comp1 Primitive Gate Primitives 1/27/06 EECS150 Lab Lecture #2 9 1/27/06 EECS150 Lab Lecture #2 10 Administrative Info Blocking vs. Non-Blocking (1) Lab Grading Get it in by the opening of the next lab Partial credit will be given for incomplete labs Please stick to one lab session Card Key Access for All is coming soon! Verilog Fragment (a) begin b = a; c = b; b <= a; c <= b; Result C = B = A B = Old A C = Old B 1/27/06 EECS150 Lab Lecture #2 11 1/27/06 EECS150 Lab Lecture #2 12 3
4 Blocking vs. Non-Blocking (2) Use Non-Blocking for FlipFlop Inference posedge/negedge require Non-Blocking Else simulation and synthesis wont match Use #1 to show causality b <= #1 a; c <= #1 b; 1/27/06 EECS150 Lab Lecture #2 13 Blocking vs. Non-Blocking (3) If you use blocking for FlipFlops: YOU WILL NOT GET WHAT YOU WANT! b = a; // b will go away c = b; // c will be a FlipFlop // b isn t needed at all c = b; // c will be a FlipFlop b = a; // b will be a FlipFlop 1/27/06 EECS150 Lab Lecture #2 14 Blocking vs. Non-Blocking (4) Race Conditions Blocking vs. Non-Blocking (5) Race Conditions file xyz.v: module XYZ(A, B, Clock); file abc.v: module ABC(B, C, Clock); input B, Clock; input C, Clock; output A; output B; reg A; reg B; A = B; module B = C; module THIS IS WRONG 1/27/06 EECS150 Lab Lecture #2 15 file xyz.v: module XYZ(A, B, Clock); file abc.v: module ABC(B, C, Clock); input B, Clock; input C, Clock; output A; output B; reg A; reg B; A <= B; module B <= C; module THIS IS CORRECT 1/27/06 EECS150 Lab Lecture #2 16 4
5 Verilog and Hardware (1) assign Sum = A + B; reg [1:0] Sum; (A or B) begin Sum = A + B; Verilog and Hardware (2) assign Out = Select? A : B; reg [1:0] Out; (Select or A or B) begin if (Select) Out = A; else Out = B; 1/27/06 EECS150 Lab Lecture #2 17 1/27/06 EECS150 Lab Lecture #2 18 Verilog and Hardware (3) assign Out = Sub? (A-B) : (A+B); reg [1:0] Out; (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; Verilog and Hardware (4) reg [1:0] Out; if (Reset) Out <= 2 b00; else Out <= In; 1/27/06 EECS150 Lab Lecture #2 19 1/27/06 EECS150 Lab Lecture #2 20 5
6 Lab #2 (1) Lab #2 (2) Lab2Top Accumulator Select Stores sum of all inputs Accumulator Written in behavioral verilog Same function as Lab1Circuit In Mux Out Peak Detector Stores largest of all inputs Peak Detector Written in structural verilog Lab2Top 1/27/06 EECS150 Lab Lecture #2 21 1/27/06 EECS150 Lab Lecture #2 22 Lab #2 (3) Lab #2 (4) Accumulator.v PeakDetector.v 1/27/06 EECS150 Lab Lecture #2 23 1/27/06 EECS150 Lab Lecture #2 24 6
7 Primitives (1) Primitives (2) wire SIntermediate, SFinal, CPropagrate, CGenerate; wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF(.Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal)); xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF(.Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal)); 1/27/06 EECS150 Lab Lecture #2 25 1/27/06 EECS150 Lab Lecture #2 26 Primitives (3) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF(.Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal)); 1/27/06 EECS150 Lab Lecture #2 27 7
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