Verilog Synthesis and FSMs. UCB EECS150 Fall 2010 Lab Lecture #3

Transcription

1 Verilog Synthesis and FSMs UCB EECS150 Fall 2010 Lab Lecture #3

2 Agenda Logic Synthesis Behavioral Verilog HDL Blocking vs. Non-Blocking Administrative Info Lab #3: The Combo Lock FSMs in Verilog HDL 2

3 Logic Synthesis Allows designing at a high level The tool handles details Very good at small-scale optimization Synthesis tool is good at small circuits Don t let it design things you can t This is not software 3

4 Behavioral Verilog (1) Specifies what a circuit does Not how it is built Most common constructs: * (posedge Clock) assign Y = 4

5 Behavioral Verilog (2) * Used to describe combinational logic. Can cause the nastiest errors Make sure no latches are generated (posedge Clock) Used to infer a register Keep these nice and short Even an accumulator is too much 5

6 Wire vs. Reg Wire Logical connection of circuit elements Cannot be assigned in an always block. Reg NOT a Register A variable used in a circuit description. Can be assigned in an always block. 6

7 Blocking vs. Non-Blocking (1) Blocking assignment = Guarantees sequential assignment Often costs unwanted hardware ONLY use in * Else simulation and synthesis won t match Non-Blocking <= All assignments happen simultaneously ONLY in (posedge Clock) 7

8 Blocking vs. Non-Blocking (2) Verilog Fragment ( * ) begin b = a; c = b; end (posedge Clock) begin b <= a; c <= b; end Effect C = B = A B = Old A C = Old B 8

9 Lab #3: The Combo Lock (1) CPU_Reset ButtonParse Reset GPIO DIP Switch C ButtonParse Reset_Lock Pushbuttons ButtonParse Enter Push A B Rotary Encoder Up Down Lab3 Counter Combination Lab3Lock State Open Rotary Encoder ResetState LEDs Used to control entry to a locked room 4bit, 2 digit combo (By Default 0x2, 0x3) Set code to 0010, Press Enter Set code to 0011, Press Enter Lock Opens (Open = 1) 9

10 Lab #3: The Combo Lock (2) READ THE LAB DO THE PRELAB 10

11 Lab #3: The Combo Lock (3) We will provide the framework You will build two modules: Lab3Lock A Moore FSM Lab3Counter An up-down counter Somewhat similar to an accumulator Use behavioral Verilog 11

12 Lab #3: The Combo Lock (4) Combination == DIGIT1 Locked Combination!= DIGIT1 Combination == DIGIT2 OK 1 Combination!= DIGIT2 Bad 1 Open Bad 2 12

13 Lab #3: The Combo Lock (5) Use LEDs and Buttons to debug Simple Hard to mess this up Great way to show state Low overhead, compared to other tools But: Can t see fast events Limited number No timing information 13

14 FSMs in Verilog Next State logic (*) block with case Register (posedge Clock) Output logic Continuous assign FSM Inputs Next State Logic Current State Next State State Current State Output Logic FSM Outputs 14

15 Acknowledgements & Contributors Slides developed by Kyle Wecker & John Wawrzynek (2/2010). This work is based closely on slides by: Chris Fletcher & Ilia Lebedev ( ) Greg Gibeling ( ) This work has been used by the following courses: UC Berkeley CS150 (Fall 2010): Components and Design Techniques for Digital Systems 15