Today. Implementation of FSMs. Designing Digital System (1) Designing Digital System (2)

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1 Today mplementation of FSMs EECS50 Spring 2006 Lab Lecture #3 Guang Yang Greg Gibeling Designing Digital System Efficient Hardware Design HDL Simulation locking vs. Non-locking dministrative nfo Lab #3: The Combo Lock FSMs in Verilog 2/3/2006 EECS50 Lab Lecture #3 2/3/2006 EECS50 Lab Lecture #3 2 Designing Digital System () High Level Design Top-Down Design Partitioning & nterfaces mplementing the Partitioned Digital Logic Start with the formal description dentify nputs Determine State Generate utputs 2/3/2006 EECS50 Lab Lecture #3 3 Designing Digital System (2) Formal descriptions Mathematical Logic Data Flow Model Petri Net Finite State Machine 2/3/2006 EECS50 Lab Lecture #3 4

2 Designing Digital System (3) Designing Digital System (4) Example: Finite State Machine K2 [pen] K Code2 & Code & Prog [Prog] nit ~Code2 & ~Code & [] D D2 [Error] <S, S 0,,, T> S: States S 0 : nitial State : nputs : utputs T: Transition Function dentify nputs What are they? Possible Values and Don t Cares Timing Process Them Raw inputs are often not what you need Might need delay/timing change Might look for a specific value/range 2/3/2006 EECS50 Lab Lecture #3 5 2/3/2006 EECS50 Lab Lecture #3 6 Designing Digital System (5) Determine States What does the module need to remember? Has it seen a particular input? How many cycles have passed? Design Memory for State Standard D Register Counter Shift Register Designing Digital System (6) Generate utputs What are they? Possible Values Timing Create the outputs They re always there Compute them from state (and inputs) Learn to think in oolean equations assign is helpful 2/3/2006 EECS50 Lab Lecture #3 7 2/3/2006 EECS50 Lab Lecture #3 8

3 Designing Digital System (7) Efficient Hardware Design () Mealy Machines C utput based on input and current state Can have major timing problems Moore Machines Mealy Machine (a or or or C) begin if (a) Z = + ; else Z = + C; Z 0 a utput based on current state Easier to work with Slightly harder to build (a or or or C) begin if (a) aux =; else aux = C; Z = + aux; C 0 aux a Moore Machine Z 2/3/2006 EECS50 Lab Lecture #3 9 2/3/2006 EECS50 Lab Lecture #3 0 Efficient Hardware Design (2) Efficient Hardware Design (3) assign = 3; assign Z = * ; assign aux = + { b0, [n-:]}; assign Z = {aux, [0]}; Z assign Z = + (2 * ); assign Z = + ( << ); assign Z = + {, b0}; 2/3/2006 EECS50 Lab Lecture #3 2/3/2006 EECS50 Lab Lecture #3 2

4 HDL Simulation () Software ased Simulation Simple and accurate llows for simulation at any precision Easy to see any signal - perfect Visibility Drawbacks Slow Simulator Depant Deadlocks are Possible! Simulation!= Synthesis HDL Simulation (2) Event Driven Simulation Virtual time axis Maintain a queue of events Pull next event off the queue Determine its consequences dd more events to the queue mplications Verilog is not executed! Things don t necessarily happen in order Verilog is SMULTED 2/3/2006 EECS50 Lab Lecture #3 3 2/3/2006 EECS50 Lab Lecture #3 4 locking vs. Non-locking () locking vs. Non-locking (2) Verilog Fragment Result Hardware (a) begin b = a; c = b; C = = C Use Non-locking for FlipFlop nference posedge/negedge require Non-locking Else simulation and synthesis wont match Use # to show causality (posedge Clock) begin b <= a; c <= b; = C = ld D Q D C Q (posedge Clock) begin b <= # a; c <= # b; Clock 2/3/2006 EECS50 Lab Lecture #3 5 2/3/2006 EECS50 Lab Lecture #3 6

5 dministrative nfo You could get checked off during your lab or during any lab T s office hours, though the T would give higher priority to his own students r in the first 0 minutes in your next lab session Try NT to get checked off in other labs. s the lab gets busier, you may not be checked off at all dministrative nfo (2) Cardkey forms distributed on 2/2 lecture See the office in Cory 253 or Soda 390 To download files from course website, cs50-temp no longer works f you cs50-xx does not work either, please David 2/3/2006 EECS50 Lab Lecture #3 7 2/3/2006 EECS50 Lab Lecture #3 8 dministrative nfo (3) Partners You MUST have one for Lab4 and later Try to keep the same one for the project You must have one in your lab section f you do not have a partner: See a T right after this lab lecture Post to the newsgroup 2/3/2006 EECS50 Lab Lecture #3 9 Lab #3: The Combo Lock () ResetCombo Reset uttons DPSwitches Code[] 0 Code[0] 0 Your Verilog Lab3Compare Lab3Top (Lab3Lock) pen Error Prog utputs Used to control entry to a locked room it, 2 digit combo (y Default, 0) Set code to, Press Set code to 0, Press Lock pens (pen = ) 2/3/2006 EECS50 Lab Lecture #3 20

6 Lab #3: The Combo Lock (2) Lab #3: The Combo Lock (3) Signal Code ResetCombo Width 2 Dir Description Code from the dipswitches button (examine the code) Reset to the default combination Example : : Press ResetCombo, Combo: 2 b, 2 b0 2: Set 2 b, Press Clock Reset pen Error System Clock System Reset, doesn t affect the combo ndicates the lock is open ndicates a bad combination 3: Set 2 b0, Press, LEDs: PEN 4: Press, LEDs: Prog 5: Set 2 b00, Press, LEDs: Prog LED 8 Reprogramming the first digit Reprogramming the second digit Use these for debugging 6: Set 2 b0, Press, LEDs: PEN 7: Combo: 2 b00, 2 b0 2/3/2006 EECS50 Lab Lecture #3 2 2/3/2006 EECS50 Lab Lecture #3 22 Lab #3: The Combo Lock (4) Lab #3: The Combo Lock (5) Example 2: : Press ResetCombo, Combo: 2 b, 2 b0 2: Set 2 b0, Press K Code & nit ~Code & D 3: Set 2 b0, Press, LEDs: Error Why doesn t Error show until step 3? Code2 & K2 [pen] ~Code2 & D2 [Error] Prog [Prog] [] 2/3/2006 EECS50 Lab Lecture #3 23 2/3/2006 EECS50 Lab Lecture #3 24

7 Lab #3: The Combo Lock (6) Lab #3: The Combo Lock (7) 0 0 Code[] Code[0] DPSwitches ResetCombo Reset Code Reset Combo CodeReg == Decode Prog Decode K2 [pen] K Code2 & Code & Prog [Prog] Code nit ~Code2 & Code2Reg ~Code & [] == Decode2 D Decode2 D2 [Error] pen Error Prog utputs Debugging with LEDs powerful way to debug Easy to understand Lower overhead than other debugging tools great way to see NextState/CurrentState Drawbacks Slow, can t see fast events No timing information, no waveform Limited number Dipswitches! 2/3/2006 EECS50 Lab Lecture #3 25 2/3/2006 EECS50 Lab Lecture #3 26 FSMs in Verilog () FSMs in Verilog (2) Mealy Machines utput based on input and current state Can have major timing problems Moore Machines utput based on current state Easier to work with Slightly harder to build Mealy Machine Moore Machine Two or Three always blocks st : CurrentState Register Clocked Handles Reset 2 nd : Generates NextState (+ utputs in Mealy) Uses CurrentState and nputs Combinational 3 rd : Generates utputs (ptional) Uses CurrentState only (for Moore Machines) Might be replaced with a few assigns 2/3/2006 EECS50 Lab Lecture #3 27 2/3/2006 EECS50 Lab Lecture #3 28

8 FSMs in Verilog (3) module MyFSM(n, ut, Clock, Reset); input n, Clock, Reset; output ut; parameter STTE_dle = b0, STTE_Run = b; STTE_X = bx; reg CurrentState, NextState, ut; (posedge Clock) begin if (Reset) CurrentState <= STTE_dle; else CurrentState <= NextState; FSMs in Verilog (4) module (CurrentState or n) begin NextState = CurrentState; ut = b0; // The case block goes here // ts on the next slide 2/3/2006 EECS50 Lab Lecture #3 29 2/3/2006 EECS50 Lab Lecture #3 30 FSMs in Verilog (5) case (CurrentState) STTE_dle: begin case if (n) NextState = STTE_Run; ut = b0; STTE_Run: begin if (n) NextState = STTE_dle; ut = b; default: begin NextState = ut = STTE_X; bx; 2/3/2006 EECS50 Lab Lecture #3 3

Verilog Synthesis and FSMs. UCB EECS150 Fall 2010 Lab Lecture #3

Verilog Synthesis and FSMs. UCB EECS150 Fall 2010 Lab Lecture #3 Verilog Synthesis and FSMs UCB EECS150 Fall 2010 Lab Lecture #3 Agenda Logic Synthesis Behavioral Verilog HDL Blocking vs. Non-Blocking Administrative Info Lab #3: The Combo Lock FSMs in Verilog HDL 2