CS Spring Combinational Examples - 1

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1 S 5 - Spring 2 - ombinational Examples - ombinational Logic esign ase Studies General esign Procedure for ombinational Logic General design procedure Examples alendar subsstem to 7-segment displa controller Process line controller Logical function unit rithmetic Integer representations ddition/subtraction rithmetic/logic units. Understand the Problem What is the circuit supposed to do? Write down inputs (data, control) and outputs raw block diagram or other picture 2. Formulate the Problem using a Suitable esign Representation Truth table or waveform diagram are tpical Ma require encoding of smbolic inputs and outputs 3. hoose Implementation Target ROM, PL, PL Mux, decoder and OR-gate iscrete gates. Follow Implementation Procedure K-maps for two-level, multi-level esign tools and hardware description language (e.g., Verilog) S 5 - Spring 2 - ombinational Examples - 2 alendar Subsstem Formalie the Problem etermine number of das in a month (to control watch displa) Used in controlling the displa of a wrist-watch L screen Inputs: month, leap ear flag Outputs: number of das Use software implementation to help understand the problem integer number_of_das ( month, leap_ear_flag) { switch (month) { case : return (3); case 2: if (leap_ear_flag == ) then return (29) else return (28); case 3: return (3); case : return (3); case 5: return (3); case 6: return (3); case 7: return (3); case 8: return (3); case 9: return (3); case : return (3); case : return (3); case 2: return (3); default: return (); } } Encoding: inar number for month: bits wires for 28, 29, 3, and 3 one-hot onl one true at an time lock diagram: month leap month leap S 5 - Spring 2 - ombinational Examples - 3 S 5 - Spring 2 - ombinational Examples - hoose Implementation Target and Perform Mapping to 7-segment displa controller iscrete gates 28 = 29 = 3 = 3 = m8 m m2 m leap m8 m m2 m leap m8 m m + m8 m m8 m + m8 m an translate to S-o-P or P-o-S month leap Understanding the problem Input is abitbcddigit(,,,) Output is the control signals for the displa (7 outputs 6) lock diagram c c5 c c6 c c2 c3 c c c2 c3 c c5 c6 to 7 segment control signal decoder S 5 - Spring 2 - ombinational Examples - 5 S 5 - Spring 2 - ombinational Examples - 6

2 x S 5 - Spring 2 - ombinational Examples - 7 Formalie the problem Implementation as Minimied -of-products Truth table Show don't cares hoose implementation target If ROM, we are done on't cares impl PL/PL ma be attractive Follow implementation procedure Minimiation using K-maps unique product terms when minimied individuall =+++'' =''++' 2=+'+ 3=''+'+'+' =''+' 5=+''+'+' 6=+'+'+' S 5 - Spring 2 - ombinational Examples - 8 Implementation as Minimied S-o-P (cont'd) PL implementation an do better 9 unique product terms (instead of 5) ' Share terms among outputs ' Each output not necessaril in minimied form 2 2 ' ' '' '' =+++'' =''++' 2=+'+ 3=''+'+'+' =''+' 5=+''+'+' 6=+'+'+' ='++''+'+ ='+''++'' 2='+'+''++' 3='+'+''+' =''+' 5='+''++' 6='+'+' ' S 5 - Spring 2 - ombinational Examples - 9 S 5 - Spring 2 - ombinational Examples - PL Implementation Production Line ontrol Limit of Product Terms per Output ecomposition of functions with larger number of terms o not share terms in PL anwa (although there are some with some shared terms) 2=+'+ Rods of varing length (+/-%) travel on conveor belt Mechanical arm pushes rods within spec (+/-5%) to one side Second arm pushes rods too long to other side Rods that are too short sta on belt 2='+'+''++' 3 light barriers (light source + photocell) as sensors esign combinational logic to activate the arms 2='+'+''+W W =+' need another input and another output Understanding the problem ecompose into multi-level logic (hopefull with support) Inputs are three sensors Find common sub-expressions among functions Outputs are two arm control signals = 3 +'' +Y = Y +'5' +''6 2 = 5 +''+' 3 = +''' ='+' Y ='' ssume sensor reads "" when tripped, "" otherwise all sensors,, ='Y +'' 5 =' +Y +' 6 = + ' 5 +'' S 5 - Spring 2 - ombinational Examples - S 5 - Spring 2 - ombinational Examples - 2

3 S 5 - Spring 2 - ombinational Examples - 3 Sketch of Problem Formalie the problem Position of Sensors to distance = specification 5% to distance = specification + 5% Truth Table Show don't cares Too Long Within Spec Too Short spec -5% spec % Function do nothing do nothing do nothing do nothing too short don't care in spec too long logic implementation now straightforward just use three 3-input N gates "too short" = '' (onl first sensor tripped) "in spec" = ' (first two sensors tripped) "too long" = (all three sensors tripped) S 5 - Spring 2 - ombinational Examples - Logical Function Unit Formalie the Problem Multi-purpose Function lock 3 control inputs to specif operation to perform on operands 2 data inputs for operands output of the same bit-width as operands 2 F choose implementation technolog 5-variable K-map to discrete gates multiplexer implementation 2 Function omments alwas + logical OR ( )' logical NN xor logical xor xnor logical xnor logical N ( + )' logical NOR alwas 3 control inputs:,, 2 2 data inputs:, output: F 2 3 8: MU S2 S S 2 F S 5 - Spring 2 - ombinational Examples - 5 S 5 - Spring 2 - ombinational Examples - 6 rithmetic ircuits Number Sstems Excellent Examples of ombinational Logic esign Time vs. Space Trade-offs oing things fast ma require more logic and thus more space Example: carr lookahead logic rithmetic and Logic Units General-purpose building blocks ritical components of processor datapaths Used within most computer instructions S 5 - Spring 2 - ombinational Examples - 7 Representation of positive numbers is the same in most sstems Major differences are in how negative numbers are represented Representation of negative numbers come in three major schemes Sign and magnitude s complement 2s complement ssumptions We'll assume abitmachine word 6 different values can be represented Roughl half are positive, half are negative S 5 - Spring 2 - ombinational Examples - 8

4 S 5 - Spring 2 - ombinational Examples - 9 Sign and Magnitude s omplement One bit dedicate to sign (positive or negative) =+ If N is a positive number, then the negative of N ( its s complement or N' ) is N' = (2 n ) N sign: = positive (or ero), = negative = Example: s complement of 7 Rest represent the absolute value or magnitude three low order bits: () thru 7 () Range for n bits +/ 2n (two representations for ) umbersome addition/subtraction must compare magnitudes to determine sign of result = = 2 = 7 = = in s complement form Shortcut: simpl compute bit-wise complement ( -> ) S 5 - Spring 2 - ombinational Examples - 2 s complement (cont'd) 2s omplement Subtraction implemented b s complement and then addition Two representations of + auses some complexities in addition + High-order bit can act as sign bit =+ + = S 5 - Spring 2 - ombinational Examples - 2 s complement with negative numbers shifted one position clockwise Onl one representation for One more negative number than positive number High-order bit can act as sign bit + + =+ = S 5 - Spring 2 - ombinational Examples s complement (cont d) 2s omplement ddition and Subtraction If N is a positive number, then the negative of N ( its 2s complement or N* ) is N* = 2n N Example: 2s complement of 7 2 = Simple ddition and Subtraction Simple scheme makes 2s complement the virtuall unanimous choice for integer number sstems in computers subtract 7 = = repr. of +() Example: 2s complement of 2 = 7 subtract = = repr. of 7 Shortcut: 2s complement = bit-wise complement + x -> + -> (representation of -7) x -> + -> (representation of 7) S 5 - Spring 2 - ombinational Examples - 23 S 5 - Spring 2 - ombinational Examples - 2

5 S 5 - Spring 2 - ombinational Examples - 25 Wh an the arr-out be Ignored? an't ignore it completel Needed to check for overflow (see next two slides) When there is no overflow, carr-out ma be true but can be ignored M + N when N > M: M* + N = (2 n M) + N = 2 n + (N M) ignoring carr-out is just like subtracting 2 n M+ NwhereN+M 2 n ( M)+( N)=M*+ N*=(2 n M)+(2 n N) =2 n (M+N) + 2 n ignoring the carr, it is just the 2s complement representation for (M + N) Overflow in 2s omplement ddition/subtraction Overflow conditions 6 dd two positive numbers to get a negative number dd two negative numbers to get a positive number = 8 = S 5 - Spring 2 - ombinational Examples Overflow onditions ircuits for inar ddition Overflow when carr into sign bit position is not equal to carr-out overflow no overflow 7 overflow 8 no overflow S 5 - Spring 2 - ombinational Examples - 27 Half adder (add 2 -bit numbers) = i' i + i i' = i xor i out=ii Full adder (carr-in to cascade for multi-bit adders) = i xor xor out=i + i + =i(+)+ i i in out i i out S 5 - Spring 2 - ombinational Examples - 28 Full adder implementations dder/subtractor Standard approach 6 gates 2 ORs, 2 Ns, 2 ORs in S Use an adder to do subtraction thanks to 2s complement representation = +( ) = +'+ ontrol signal selects or 2s complement of lternative implementation 5 gates half adder is an OR gate and N gate in out out = +in(xor)=+in+in 2 ORs, 2 Ns, OR xor xor xor in Half Half dder dder out out in ( xor ) 3 33' out in Sel 2 22' out in ' out in ' Sel Sel out in S3 S2 S S Sel dd' Subtract in S 5 - Spring 2 - ombinational Examples - 29 out Overflow S 5 - Spring 2 - ombinational Examples - 3

6 S 5 - Spring 2 - ombinational Examples - 3 Ripple-arr dders Ripple-arr dders ritical ela late arriving signal The propagation of carr from low to high @ two gate delas to compute out in 2 stage adder ritical dela The propagation of carr from low to high order stages + is the worst case addition arr must propagate through all bits S, Valid S, 2 Valid S2, 3 Valid S3, Valid 3 3 T T2 T T6 T8 S 5 - Spring 2 - ombinational Examples - 32 arr-lookahead Logic arr-lookahead Logic (cont d) arr generate: Gi = i i Must generate carr when = = arr propagate: Pi = i xor i arr-in will equal carr-out here and out can be re-expressed in terms of generate/propagate: Si = i xor i xor i = Pi xor i i+ = i i + i i + i i = i i + i (i + i) = i i + i (i xor i) =Gi+iPi Re-express the carr logic as follows: =G+P 2=G+P=G+PG+PP 3=G2=G2+G+PG+PP =G3+P33=G3+P3G2+P3G+P3PG +P3PP Each of the carr equations can be implemented with two-level logic ll inputs are now directl derived from data inputs and not from intermediate carries this allows computation of all sum outputs to proceed in parallel S 5 - Spring 2 - ombinational Examples - 33 S 5 - Spring 2 - ombinational Examples - 3 arr-lookahead Implementation arr-lookahead Implementation (cont d) dder with propagate and generate outputs i i i Pi@gatedela Si@2gatedelas Gi@gatedela increasingl complex logic for carries arr-lookahead logic generates individual carries s computed much more quickl in parallel However, cost of carr logic increases with more stages in in P G P P G P G 2 P P G P G G2 P P P3 G P 3 P3 G P3 G2 P3 G S 5 - Spring 2 - ombinational Examples - 35 S 5 - Spring 2 - ombinational Examples - 36

7 S 5 - Spring 2 - ombinational Examples - 37 arr-lookahead dder with ascaded arr-lookahead Logic arr-select dder arr-lookahead adder Redundant hardware to make carr calculation go faster four-bit adders with internal carr lookahead ompute two high-order sums in parallel while waiting for carr-in Second level carr lookahead unit extends lookahead to 6 bits One assuming carr-in is and another assuming carr-in is Select correct result once carr-in is finall computed [5-2][5-2] -bit dder P G 2 [-8] P [-8] -bit dder G 8 [7-] P [7-] -bit dder G [3-] P [3-] -bit dder 8 -bit adder [7:] adder bit adder [7:] adder low P3 G3 3 G2 2 P G P G Lookahead arr five 2: mux -it dder [3:] 8 S7 S6 S5 S S3 S2 S S S 5 - Spring 2 - ombinational Examples - 38 rithmetic Logic Unit esign Specification rithmetic Logic Unit esign (cont d) M =, logical bitwise operations S S Function omment Fi=i input i transferred to output Fi = not i complement of i transferred to output Fi=ixori compute OR of i, i Fi = i xnor i compute NOR of i, i M =, =, arithmetic operations F= input passed to output F = not complement of passed to output F = plus sum of and F = (not ) plus sum of and complement of M =, =, arithmetic operations F = plus increment F = (not ) plus twos complement of F = plus plus increment sum of and F = (not ) plus plus minus logical and arithmetic operations not all operations appear useful, but "fall out" of internal logic Sample LU truth table M S S i i i Fi i+ S 5 - Spring 2 - ombinational Examples - 39 S 5 - Spring 2 - ombinational Examples - rithmetic Logic Unit esign (cont d) rithmetic Logic Unit esign (cont d) \S \i M S i S i Sample LU multi-level discrete gate logic implementation [35] M i i [33] \o i [3] o [33] [3] [33] [33] \o M [3] i [35] [3] [3] \o \[3] \[35] 2 gates Fi Sample LU clever multi-level implementation S i S i M i first-level gates use S to complement i S = causes gate to pass i 2 S = causes gate to pass i' use S to block i S = causes gate to make i go forward as (don't want i for operations with just ) S = causes gate to pass i use M to block i 2 M = causes gate 2 to make i go forward as (don't want i for logical operations) M = causes gate 2 to pass i other gates for M= (logical operations, i is ignored) 3 Fi = S i xor (S xor i) =S'S'(i)+S'S(i')+ S S' ( i i' + i' i ) + S S ( i' i' + i i ) for M= (arithmetic operations) Fi=Sixor((Sxori)xori)= 3 O i+=i(sxori)+si((sxori)xori)= i+ Fi just a full adder with inputs S xor i, S i, and i S 5 - Spring 2 - ombinational Examples - S 5 - Spring 2 - ombinational Examples - 2

8 S 5 - Spring 2 - ombinational Examples - 3 mar for Examples of ombinational Logic ombinational logic design process Formalie problem: encodings, truth-table, equations hoose implementation tech (ROM, PL, PL, discrete gates) Implement b following the design procedure for that technolog inar number representation Positive numbers the same ifference is in how negative numbers are represented 2s complement easiest to handle: one representation for ero, slightl complicated complementation, simple addition ircuits for binar addition asic half-adder and full-adder arr lookahead logic arr-select LU esign Specification, implementation