MCQ's on Unit-3 Control Unit

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Christine Johnson
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1 * indicates questions for reference only & not included in syllabus Sr.No. Question Option a b c d generates Accepts Stores data input data 1 The Control unit of a computer in the signals to from the memory execute an keyboard 2 Execution of a program statement involves To execute machine a set of in a proper sequence must be performed register to register data transfer data transfer from register to external perform arithematic & logical on data programs s s Basic task for unit is Sequencing execution Generation of appropriate signals to execute a series of s in proper sequence is done by Sequencing execution ALU CPU 6 Execution task of unit is responsible for Executing program Executing an Executing all of the s Executing each It helps in 7 avoiding the Z register stores the output of ALU & loop back helps in hence result pipelining 8 the MAR<--PC is fetch the fetch the executed to data 9 In single bus organization, the external bus connected to CPU via PC & IR MDR & MAR AC & ALU MAR & PC 10 External bus connects CPU to memory I/O devices MDR MCQ's on Unit-3 Control Unit The advantage of using internal bus organization is Saving CPU space Simple data path interconnec tions A is a performed by machine on the data stored in the registers task primitive action

2 Micro s can be For implementing machine a set of must be executed in predefined sequence Register transfer Arithmetic logic all of the program an To transfer the contents from register R1 to R2 identify the sequence of s 1. Set R/W signal to 0 2. move data from internal CPU bus to R1 3.Put the data on internal CPU bus 4. read Register R1 4,3,1,2 1,2,3,4 3,4,2,1 2,3,1,4 For R3<-R1+R2, s are R1<-Y, Z<- Y+R2, R3<-Z Y<-R1, Z<- Y+R2, R3<-Z R1<-Y, Y+R2<-Z, R1<-Y, Z<- Y+R2, Z<-R Shift s are Circular Logical Arithmetic all of the Rotate Right Rotate left by 3 RORR1,3 means Rotate Right Rotate left by 3 bits bits Fetch the Fetch the, operand, Fetch the Fetch the Asimple execution cycle consist operand,, of steps Execute Execute all of the What is the purpose of PC <-PC+1 Steps required forfetch cycle are Hardwired unit is implemented as in programmed unit, s are stored in special memory called Hardwired unit uses to interpret an 25 While designing hardwired unit factor to be considered Fetch & execute To store next MAR<-PC, MDR<- M(MAR),PC <-PC+1, MDR<-IR Sequential logic To fetch next MAR<-PC, MDR<- M(MAR),PC <-PC+1, IR<- MDR finite state machine To execute next MAR<-PC, M(MAR)<- MDR,PC <- PC+1, IR<- MDR all of the PC<-MAR, M(MAR)<- MDR,PC <- PC+1, IR<-MDR memory RAM ROM memory Special Special Program fixed logic register amount of hardware Speed of cost of used design all of the 26 state table method is the method for Hardwired programme designing unit d 27 In state table method it minimize the amount of software hardware

3 28 29 Delay element method uses for timing signals T flip flop D flip flop SR flip flop JK flip flop Programma Programma ble Logic Programme ble Logical Programme PLA is Array Logic Array Array Logical Array 30 In state transition table, unit transmits from one state depending on its Identify the correct statement for using delay element Microprogram consisting of is stored in memory of unit signals are generated by execution of Current state Every state requires delay element s s Input to the ler The signals that activate A decision same box can be implemente signals are d by two 2- Ored to get input AND one gates s program s program s program macro program program A sequence of s is called s A can causeexecution of one or more s oneor more address of next to to A consists of be executed be executed Micro programmed unit is flexible than hardwired unit TRUE FALSE Micro programmed unit is slower than hardwired unit TRUE FALSE all of the macro program macro program macro program s oneor more macro to be executed 39 It is easy to handle complex s in case of hardwired unit TRUE FALSE 40 Micro s are divided into Horizontal vertical abov 41 Input to unit IR ALU flags Clock all of the 42 To fetch an operand addressed using direct addressing, the executed is. MAR<-PC MAR<-M(MDPc<-PC+1 abov 43 delay element method used to design Hardwired unit programme d

4 A hardwired A has Vertical s are characterized by Horizontal s are characterized by The machine consists of 49 s are used to bring data to and from registers is faster than programme d unit Control field Short formats facilitates easy implementa tion ofnew s address field considerabl e encodingof the high degree long formats of parallism Reference to source OPCode code data arithmetic & transfer logic s s is useful in implementin g most frequently used s little encodingof the information referenceto destination operand transfer s both a & c all of the all of the Miscellenious s register transfermicr arithmetic logic is a type of o all of the For memory transfer s register provides the address on address bus MBR MAR IOAR IOBR For memory transfer s register is used to access data on thedata bus MBR MAR IOAR IOBR The signals generated for Pcout, Pcin, the MAR<-PC are MARin Pcin, MARin MARout Pcout, MARout 54 The signals for MDR<- M(MAR) are MARout, RAM out, MDR in Pcout,ALUin,INC, Zout,Pcin The signals for PC<-PC+1 Micro programming can be used for high level language support TRUE FALSE Microprogramming can be used for Emulation MARout, MARin, RAM RAM in, out, MDR in MDR in Pcout,ALUo Pcout,ALUin ut,inc,,inc, Zout,Pcin Zin,Pcin Operating system support realization of special purpose devices MARout, RAM out, MDRout Pcout,ALUin,IN C, Zout,Pcout all of the

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The Processing Unit. TU-Delft. in1210/01-pds 1

The Processing Unit. TU-Delft. in1210/01-pds 1 The Processing Unit in1210/01-pds 1 Problem instruction? y Decoder a ALU y f Reg in1210/01-pds 2 Basic cycle! Assume an instruction occupies a single word in memory! Basic cycle to be implemented: 1. Fetch