Unit 8 - Week 7: Organization and Optimization of Micro-programmed Controlled Control Unit

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1 X Courses» Computer Organization and Architecture: A Pedagogical Aspect Announcements Course Ask a Question Progress Mentor Unit 8 - Week 7: Organization and Optimization of Micro-programmed Controlled Control Unit Course outline How to access the portal Assignment for Week 7 The due date for submitting this assignment has passed. Submitted assignment Due on , 23:59 IST. Week 1: Fundamentals of Digital Computer 1) For a CPU with single bus organisation, as shown below, the control steps for completely executing an instruction LOAD R1, #32 (with immediate addressing mode) are: Week 2: Fundamental of Digital Computer Week 3: Modes, Instruction Set and Instruction Execution Flow Week 4: Modes, Instruction Set and Instruction Execution Flow Week 5: Modes, Instruction Set and Instruction Execution Flow Week 6: Organization and Optimization of Microprogrammed Controlled Control Unit A project of 2014 NPTEL - Privacy & Terms - Honor Code - FAQs - In association with Funded by 1 of 6 Tuesday 15 May :52 PM

2 Unit Handling Different Modes Handling Control Transfer Instructions Design of Hardwired controlled Control Unit Quiz : Assignment for Week 7 Week 8: Organization and Optimization of Microprogrammed Controlled Control Unit Week 9: Memory Sub-system Organization Week 10: Memory Sub-system Organization Week 11: Memory Sub-system Organization Week 12: Input/output Subsystem 5) WMFC Powered by 6) MDR out, Y in, Select=1, Add 7) R1 out, Z in 8) Z out, R1 in None of the above 4) IR out, R1 in 2) The step IR <- Memory[PC] explains : Instruction fetch step Instruction decode step Instruction execute step None of the above Instruction fetch step 3) For a CPU with single bus organisation, the control steps for completely executing an instruction ADD R1, M (where, M is a memory location) (with direct addressing mode) are: 4) IR out, R1 in 1)PC out, MAR in, Read, Select=0, Add, Z in 4) IR out, MAR in, Read 5) WMFC 6) MDR out, Y in, Select=1, Add 7) R1 out, Z in 8) Z out, R1 in None of the above 2 of 6 Tuesday 15 May :52 PM

3 1)PC out, MAR in, Read, Select=0, Add, Z in 4) IR out, MAR in, Read 5) WMFC 6) MDR out, Y in, Select=1, Add 7) R1 out, Z in 8) Z out, R1 in 4) Which of the following is wrong? Control path commands the data path, memory and I/O Data path commands the control path and sends the control signals to the control path Data path performs arithmetic operations and holds data Control unit sends control signals to different modules to select the functionality of the modules Data path commands the control path and sends the control signals to the control path 5) For a CPU with single bus organisation, as shown below, the control steps for completely executing a jump on Zero instruction JMPZ 3200 are: 3 of 6 Tuesday 15 May :52 PM

4 4) Offset-field-of-IR out, Select=1, Add, Z in, If Sign Flag!=0 then END 4) IR out, R1 in 6) Which of the following is wrong about hardwired control unit? The hardwired control unit is a Finite State Machine based controller Hardwired control unit is faster in execution compared to micro programmed control unit For each control step, the hard-wired control unit needs to assert signals on different lines on the various components of the CPU None of these None of these 7) The major disadvantage of hardwired control unit is : Hardwired control unit is faster in execution compared to micro programmed control unit The instruction set and the control logic are directly tied together by hardcoded circuits that cannot be altered. The state machine is implemented as a fixed sequential circuit. Generate the specific fixed sequences of control signals only. The instruction set and the control logic are directly tied together by hardcoded circuits that cannot be altered. 8) For a CPU with single bus organisation, the control steps for completely executing an unconditional jump instruction JMP 3200 are : 2. Z out, PC in, Y in, WMFC 4. Offset-field-of-IR out, Select=1, Add, Z in, If Zero Flag!=0 then END 5. Z out, PC in 2. Z out, PC in, WMFC 4. IR out, MAR in, Read 5. WMFC 6. MDR out, Y in, Select=1, Add 4 of 6 Tuesday 15 May :52 PM

5 7. R1 out, Z in 8. Z out, R1 in 2. Z out, PC in, WMFC 4. IR out, R1 in 2. Z out, PC in, Y in, WMFC 4. Offset-field-of-IR out, Select=1, Add, Z in 5. Z out, PC in 2. Z out, PC in, Y in, WMFC 4. Offset-field-of-IR out, Select=1, Add, Z in 5. Z out, PC in 9) Given below is the FSM for the hardwired control unit for instruction JMPZ M (Jumps conditionally if zero flag is set to the instruction in memory location M i.e., update the value of PC to M). Which of the options given below appropriately labels the transition from S2 to S3 (marked as in the figure)? T3/MDR out =1, IR in =0 T3/MDR out =0, IR in =0 T3/MDR out =1, IR in =1 T3/MDR out =0, IR in =1 5 of 6 Tuesday 15 May :52 PM

6 T3/MDR out =1, IR in =1 Previous Page End 6 of 6 Tuesday 15 May :52 PM

The due date for submitting this assignment has passed. 1) Which of the following statements regarding a microcomputer, a

The due date for submitting this assignment has passed. 1) Which of the following statements regarding a microcomputer, a and Microcontrollers - - Unit 3... X reviewer2@nptel.iitm.ac.in Courses» and Microcontrollers Unit 3 - Week 2 Announcements Course Ask a Question Progress Mentor Course outline How to access the portal