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Boolean Resubstitution With Permissible Functions and Binary Decision Diagrams Hitomi Sato* 1, Yoshihiro Yasue* 1, Yusuke Matsunaga*2 and Masahiro Fujita*2 * 1: Semiconductor Division, FUJITSU

1 Boolean Resubstitution With Permissible Functions and Binary Decision Diagrams Hitomi Sato* 1, Yoshihiro Yasue* 1, Yusuke Matsunaga*2 and Masahiro Fujita*2 * 1: Semiconductor Division, FUJITSU Limited, Kawasaki Japan *2: AI Laboratory, FUJlTSU Labs. Limited, Kawasaki Japan In this paper, we present a new Boolean resubstitution technique with permissible functions and ordered binary decision diagrams, abbreviated as OBDD[8]. Boolean resubstitution is one technique for multi-level logic optimization. Permissible functions are special don't care sets. We represent the data structure of permissible functions and logic functions at each node in Boolean networks in terms of OBDD. Therefore, logic functions can be flexibly manipulated and rapidly executed. We have previously reported a multi-level logic optimization technique called transduction methods[l] using OBDD in ICCAD'89[7]. We have improved the OBDD operation techniques, so that now OBDD operations can be executed faster than we reported before. We also applied Boolean resubstitution to our multi-level logic synthesis. We present results of experiments employing the improved OBDD operation techniques and applying Boolean resubstitution to our multi-level logic synthesis. 1. INTRODUCTION In logic synthesis, multi-level logic optimization is important to obtain high quality synthesized circuits with regard to area and testability. some multi-level logic optimization techniques have been proposed[ 1,2,4,5,6,7]. The key to optimization is the use of don't cares. Many optimization techniques use don't cares, some directly and some implicitly[9]. Two of these techniques used in multi-level logic synthesis are node minimization [2,4,5,61 and transduction methods[l,7]. Node minimization is done using a two-level minimizer (such as ESPRESS0[3]). The objective is to utilize the implicit don't care conditions that exist at each node in a Boolean network to perform two-level logic minimization on the Boolean function associated with that node. Unfortunately, the entire don't care set is usually extremely large, so that the use of the entire don't care set consumes a large amount of CPU-time and memory. Two heuristic approaches, called Bold[5,61 and MIS[2,4], have been studied to approximate the practical CPU-time and memories for practical circuits. The Bold heuristic is a tautology-based approach that directly uses multi-level equivalence and tautology checking algorithms. The advantage of this approach is that all don't care conditions are automatically accounted for, so the optimizer is able to account for all optimization degrees of freedom. The MIS heuristic is a don't care approach that employs the complete power of the ESPRESS0[3] minimization heuristics. However, the don't care sets are approximated, and, hence, some of the optimization degrees of freedom are sacrificed, and a sub-optimal solution is obtained. Both approaches are being continually improved. Transduction means transformation and reduction. Transduction methods were proposed by Muroga and his students in the mid '7Os[l]. These methods also use the don't care sets, called permissible functions. Permissible functions are observable don't care sets of a node in the circuit networks and are used to check the possibility of the transformation or reduction operations. The original transduction methods[ 13 represented the data structure of logic functions and permissible functions in terms of truth tables, so that large amounts of CPU-time and memory were required. We reported transduction methods representing the data structure of logic functions and permissible functions in terms of OBDD in ICCAD'89[7]. Logic functions are represented very compactly with OBDD, therefore the operations of logic functions are executed quickly and large Boolean functions can be executed. Boolean resubstitution is implemented in the Bold[Sl step. This resubstitution generalizes the REDUCE, EXPAND and IRREDUNDANT operations[3] to a multilevel context. In this operation, logical redundancies are removed, and the network configuration can be modified, resulting in possibilities for further optimization. We implemented the Boolean resubstitution with permissible functions and OBDD, and merged the Boolean resubstitution with the weak division procedure in our multi-level logic synthesis. We also have improved the OBDD operation techniques to yield fast execution of logic function manipulations. 2. PERMISSIBLE FUNCTIONS AND OBDL 2.1 Permissible functions The key concept of permissible functions is that each node in a circuit network is an incompletely-specified function of the primary inputs, and permissible functions represent possible implementations at such nodes. These permissible functions are sets of logic functions that do not change any output logic, and they are defined as follows: Assume Vi is an intermediate node in a network. The logic function of any output variable in the network may not change even when the logic function Fi of node Vi is th ACMllEEE Design Automation 1990 IEEE X/90/0006/0284 $1.OO

2 replaced with another logic function PF. Then the logic function PF is a permissible function of node Vi. Permissible functions are computed at each node, input variable, or gate in the network. When only two nodes are connected, the permissible functions of these two nodes are identical. While when more than two nodes are connected, the permissible functions of each node are not identical. Usually, there is more than one permissible function for each node. Therefore, the don't Care mark(*) is used to represent a set of permissible functions as a single vector at that node. Fig.1 shows an example of permissible functions. In this figure, VI and v2 are input nodes, v4 is an output node, and v3 is an intermediate node. The Fi vector in the truth table represents a logic function of each node vi. G4 is an OR gate. Since the first and second values of F4 are Os, the first and second values of F3 must remain as Os. The third and fourth values of F4 are 1s and the third and fourth values of FI are 1s. Thus, the third and fourth values of F3 may be either 0 or 1, and the logic function of F4 does not change even when logic function F3 is replaced with PF3. Then PF3 is the set of permissible functions of V3. Though the logic functions and permissible functions in this figure are represented in terms of truth tables, in our program these logics are represented in terms of OBDD. Boolean resubstitution uses the following two conditions: 1) Pruning condition The connection whose set of permissible functions consists of 1 and don't care only, or 0 and don't care only, can be set to constant 1 or 0. Then this connection may be removed from the network. 2) Connectable condition A connection can be added to a gate as a new fan-in when the new logic function of that gate's output is included in its set of permissible functions. The set of all possible permissible functions at any node can be consequently expressed by a single vector. This set is called the Maximum Set of Permissible Functions, abbreviated as MSPF[l]. The MSPF is usually unique to a network and only one node can be changed at a time. Therefore, the MSPFs must be recalculated for each transformation or reduction operation. In contrast, those permissible functions defined as other parts of the logics that can be changed at a time are called the Compatible Set of Permissible Functions. abbreviated as CSPF[ 11. The CSPF is a sub-set of the MSPF. The CSPF is not unique to a network. 2.2 Ordered Binary Decision Diagrams Ordered Binary Decision Diagrams, abbreviated as OBDD, were proposed by Bryant of CMU[81. An OBDD is a data structure for representing Boolean functions with restrictions on the ordering of variables in the graph. Boolean functions are represented by directed, acyclic graphs with a vertex set containing two types of vertices. A non-terminal vertex has as attributes an input variable index and two children. A terminal vertex has as attributes a value 0 or 1. Ordered means that if xi<xj then all nodes with xi precede all nodes with xj. A path from the root to the terminal vertex with value O( or 1) gives a condition when Boolean function f = O( or f = 1). The graph size depends on the variable ordering. For good ordering, OBDDs remain reasonably small for Boolean functions. Table-1 shows the basic operations on OBDDs. The reduce procedure transforms an arbitrary graph into a reduced graph denoting the same function. Given variable ordering, a reduced OBDD is canonical. The procedure apply provides the basic method for creating the representation of a function according to the operations in a Boolean expression or logic gate network. Refer to [8] for the details of operations on OBDDs. Fig.2 shows an example of OBDD representation of a Boolean function F=vl&v2 + v3. In this figure, a rectangle indicates a terminal node with logical values, and a circle indicates a non-terminal node containing the variable index with the two children indicated by branches labeled 0 and 1. The variable ordering of this graph is VI > v2 >v3. W I PF3 = I OO** 1 Reduce I APP'Y Graph reduced to canonical form I Flcop>F2 n I PF3 is a set of permissible functions Fia.1 An FxamDle of Permissible Functions Fia.2 OBDD Representation of F=vl &v? + v9 285

3 3. OBDD IMPROVEMENTS 3.1 Simultaneous positive and negative judgment of logic The connectable condition of whether a negative or positive connection can be added is checked simultaneously. We calculate both positive and negative logic values during the apply procedure, so that the number of operations on an OBDD is reduced. 3.2 Sharing graph and using negative edges A graph can be shared with many logic functions and permissible functions, and the negative edge can be used to indicate an inverted logic. This improvement enables the graph to be copied only by operating the pointer. The effective use of graph sharing and negative edges reduces CPU-time and memories. Fig.3 contains an example of a shared OBDD with negative edges. FI., (1 \ Ordered BDD - I2IShared OBDD 3.3 Non-terminal nodes classification Terminal nodes of original OBDD[8] have only the values 0 or 1, and non-terminal nodes have only don't care value. However, permissible functions have a don't care value in addition to 0 and 1. Therefore, we represent the terminal node with three values, 1,O and don't care. Then, non-terminal nodes can be classified as follows: group-1: Having only 0 and don't care values and group-1 as children. group-2: Having only 1 and don't care values and group-2 as children. group-3: Having only 0 and 1 values and group-3 as children. group4 Others. The original apply procedure[8] should be modified according to this classification. This modification will increase the chance of finding operation results at nonterminal nodes and make it possible to complete searching quickly. -(3)Shared OBDD with negative edges F1 and F2 are the following functions: F1 = "(a@b), F2 = a@b. Here notation means mean Exclusive OR. In figure (3), edges with small circle indicate negative edges. 3- Fn. 4. BOOLEAN RESUBSTITUTION WITH PERMISSIBLE FUNCTIONS AND OBDD We have implemented Boolean resubstitution based on the Bold algorithm[5] with permissible functions. Boolean resubstitution generalizes the REDUCTION, EXPAND and IRREDUNDANT operations[3] to a multilevel context. This process removes the redundancies from the network, as well as modifications the network configuration. Thus. the possibilities of further optimization are increased. Fig.4 shows the general flow of our Boolean resubstitution. Even though we are manipulating Boolean networks, each cover comprises connections of AND gates and one OR gate. We use the following conditions to execute operations (l), (2) and (3) shown in Fig.4. Condition-(1): CV1 is not a transitive fan-in of CV2. Condition-(2): When the following condition for connection is satisfied, CVZ can be connected to gate G. After the negative or positive connection from CVI is added to an AND gate G in CV2, the new logic function of G is still included in the permissible functions of gate G. Condition-(3): When the following pruning condition is satisfied, a connection can be removed from G. The connections whose permissible functions consist of only 1 and don't care, or 0 and don't care, set to be constant value 1 or

4 An example of how Boolean resubstitution is implemented with CSPFs is shown in FigS. When there are two Boolean functions such as the followingfand g. f is substituted with g by Boolean resubstitution. Here we assume that f is a primary output variable, and g is an intermediate variable. Then the logic function off becomes the permissible function off itself. In Fig.5, Fi indicates the logic function of variable i, and PFi indicates the CSPF of variable i. Notation & indicates logical AND, + indicates logical OR, and indicates logical NOT. f = a&(%+c) + b&c, g=a+b. Boolean functionfis substituted with g. f = g&(% +e). The processing flow on this Boolean network is as follows: 1: First, the logic function and CSPFs of each node in the network are calculated( see Fig.5-( 1)). 2: Here we assume that CVI and CV2 are selected as in Fig.5-(1), CVI comprises a single OR gate and CV2 comprises two AND gates and one OR gate. 3: We try to add the connection from gate G5 to the fanin of G2 in CV2. The new logic function of G2 becomes [OOOOllOl], which is included in the set of permissible functions, PF2=[000*11011, of gate G2. Thus, the connection from G5 can be added to the fan-ins of G2. 4: Here we recalculate the new permissible functions of each fan-in of G2. The permissible functions of fan-in a of G2 become PFa=[****ll*ll. PFa can be replaced with the constant value 1, so this fan-in can be removed (see Fig.5-(2)). 5: Similarly, the connection from G5 can be added to the fan-ins of G3. and fan-in b of G3 can be removed. 6: Here we recalculate the logic functions of gate G2 and G3 and the permissible functions of each fan-in of G4. The permissible functions of the connection from G3 become PF3=[OOO***O*]. PF3 can be replaced with the constant value 0, so this connection can be removed from G4. G4 can also be removed(= Fig.5-(3)). 7: These processes result in the logic function f with expression of g (see Fig.5-(4)). U) Calculate loaic functions a nd CSPFs - - CV1 I--- The new CSPFs of each f -' a Of G7 PF5 = [00**11*1] PFa= [****ll*l] :..E PFl = [**0*1101] PFa => constant 1 f = a&("&) + b&c The new loaic functions and CS PFs in CV2 NewF2=[OOO New PF2 = [ ] New F3 = [OOOlOlOl] New PF3 = [000***0*] => constant 0 14) Result of Boolean resubstitutim Boolean resutstitution( ) P CVl and CV2 Coven in the Boolean network */ PG :And gate in a cover CV2 *I ( fa each COVCI CV1( (1) for each cover cv2( for each AND gate G in CV2( (2) try to m a t CV1 to G; P Reduction *I (3) iry to remove other fan-ins from G; P Expand *I 1 iry to remove gates in (32; P Irredundant *I a n h -4 I- C.. Fia.5 Flow of Boolean resubstitutioq g Fia.4 General flow of Boolean resubtitutioq 287

5 5. EXPERIMENTAL RESULTS This section presents the results of our experiments employing improved OBDD operation techniques and applying Boolean resubstitution to our multi-level logic synthesis. 5.1 Results of improvements of OBDD operation techniques We investigated transduction procedures using the improvements of OBDD operation techniques. We compared the results reported in ICCAD'89[7] with the new results, as shown in Table-2. Each column at CPUtime of Table-2 indicates the following: A: Not improved. B: Simultaneous positive and negative logic judgement. C: Above B plus the classification of non-terminal nodes. D: Above C plus shared graphs with negative and positive edges. The differences in the OBDD operation techniques do not affect the optimization results. The processing speed increased about 10% to 20% with each improvement and the CPU-time for total improvements was halved. 5.2 Results of Boolean resubstitution Weak division and Boolean resubstitution were merged and executed iteratively, and we investigated the merged program. The threshold value of decreasing costs for one weak division processing was determined automatically during the first execution loop. Our results(0urs) are compared with the results of MIS2.1 and Bold in Table-3. The results for MIS2.1 were reported in the MCNC'89 workshop poster session[* 13. Each MIS2.1 column indicates the following: Single is the factored form literal count using a single execution of a standard script. CPU-time is the time in seconds on a DEC 3100 workstation for the single script. Best is the best factored form literal count using several executions of a standard script. Literals at Bold were reported in references[5]. Literals at OURS were literal count using a single execution of a merged program, weak division and Boolean resubstitution. CPU-time at OURS is the time in seconds on SUN SPARCstationl workstation. DEC 3100 is about 14 MIPS and SUN SPARCstationl is about 12.5 MIPS. As shown in Table-3, our technique produced smaller literal count than those of single MIS2.1 execution. The results of our literal count were similar to those of MIS2.1 Best and Bold, except for alu4. These results are within about 10%. For alu4, however, the number of literals that can be produced by our technique is about half that of MIS2.1 Best. Thus the result of CMOS technology mapping to this optimized ah4 Boolean network is in good comparison with the manual design. shown in Table-3, with regard to optimization quality and execution time. It is still possible, however, to further reduce the execution time. We intend to continue our work on improving OBDD manipulation techniques. REFERENCES [l] S.Muroga, YXambayashi, H.C.Lai and J.N.Culliney,"The transduction method-design of logic networks based on permissible functions," IEEE TC,October 1989, Vo1.38, No.10, pp [2] R.K.Brayton, R.Rudel1, A.Sangiovanni-Vincentelli and A.R.Wang," MIS: Multi-level interactive logic optimization system," IEEE TC., Vol.CAD-6(6), November 1989, pp [3] R.K.Brayton, G.D.Hachte1, C.McMullen and A.Sangiovanni-Vincentelli, "Logic minimization algorithms for VLSI synthesis," Kluwer Academic Publishers, Boston, [4] Allex Saldanha, Albert Wang, R.Brayton and A. S a ng io v a n n i - V in c en te 11 i," Mu 1 ti - 1 eve 1 1 og i c simplification using don't care filters," ACM/IEEE DAC, June 1989, pp [5] D.Bostick, G.D.Hachte1, R.Jacoby, M.R.Lightner, P.Moceyunas, C.R.Morrison, D.Ravenscroft." THE BOULDER OPTIMAL LOGIC DESIGN SYSTEM," IEEE ICCAD, 1987, pp [6] G.Hachte1, R.Jacoby, P.Moceyunas and C.Momson," Performance Enhancements in BOLD using "implications"," IEEE ICCAD, November 1988, pp [7] Y.Matsunaga and M. Fujita," Multi-level logic optimization using binary decision diagrams," IEEE ICCAD, November [8] R.E.Bryant,"Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computer, August 1986, ~~ [O] Robert K. Brayton,"Multi-level Logic Synthesis," ICCAD-89 Tutorial, November CONCLUSIONS Boolean resubstitution with permissible functions and OBDD is presented. The results of this technique are especially suitable for large examples, such as ah4 288

6 Table.2 Results of immovements of OBDD Techniques Circuit name rd53 misex 1 misex2 rd73 5xpl rd84 start n - D Table3. CO mdarison of our Results (Number of literals) MIs2.1 [*l] Bold[5] OURS Vame ingle terals CPU-time seconds est terals Literals Literals CPU-time seconds 11u4 ;lip hke2 nisexl nisex2 xisex3 nisex3 :d53 rd7 3 -d84 vg2 5XPl * 1 : MCNC'89 workshop poster session 289

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2 Synthesis The Y-diagram Revisited Structural Behavioral More abstract designs Physical CAD for VLSI 2 1 Structural Synthesis Behavioral Physical CAD for VLSI 3 Structural Processor Memory Bus Behavioral