Representations of Terms Representations of Boolean Networks
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1 Representations of Terms Representations of Boolean Networks Logic Circuits Design Seminars WS2010/2011, Lecture 4 Ing. Petr Fišer, Ph.D. Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Evropský sociální fond Praha & EU: Investujeme do vaší budoucnosti
2 Outline Combinational circuits are assumed 2-level representations (SOP, CNF, ) Truth table Ternary tree (trie) Multi-level network representations General network AIG PI-SCN-4, ČVUT FIT, Petr Fišer,
3 Function Representations Zoo Sum-of-Products (SOP) E.g. ab + bc + cd Product-of-Sums (POS, CNF) E.g. (a + b ).(b + c ).(c + d) Disjoint Sum-of-Products (DSOP) E.g. ab + bc + bcd + a b cd SOP terms are mutually disjoint (any two terms have empty intersection) EXOR Sum-of-Products (ESOP) E.g. ab cd bc XOR instead of OR Also called Reed-Muller expressions Sum of Pseudoproducts (SPP) E.g. (a d)(b c) + a(b d ) Sum of products of XORs 3-level PI-SCN-4, ČVUT FIT, Petr Fišer,
4 Truth Table (SOP, POS, ESOP, ) Possible term encodings: 1. One char for one literal ( 1, 0, X ) + Fast random access - Big memory wasting (3 out of 256 symbols used = 1.17% efficiency) 2. Bit-parallel representation Minterms: 32 (64) variables per machine word More-dimensional terms: 32 (64) variables per 2 words Example: f(a, b, c) = a b = (01X) = (010), (001) + Much less memory wasting (3 out of 4 symbols) + Parallel execution of arithmetic operations (one instruction) - Slower random access (but only logic operations are necessary to address one bit) PI-SCN-4, ČVUT FIT, Petr Fišer,
5 Truth Table (SOP, POS) Bit-parallel representation + Parallel execution of arithmetic operations Example of encoding: literal 0 : [v, d] = [0, 0] literal 1 : [v, d] = [1, 0] literal X : [v, d] = [0, 1] Example of Boolean operations: t 3 = t 1 AND t 2 : t v 3 = t v 1 & t v 2 t d 3 = (t d 1 & t 2d ) (t d 1 & t 2v ) (t v 1 & t 2d ) Many logic operations big minus PI-SCN-4, ČVUT FIT, Petr Fišer,
6 Trie In computer science, a trie, or prefix tree, is an ordered tree data structure that is used to store an associative array where the keys are usually strings. The term trie comes from "retrieval. Following the etymology, the inventor, Edward Fredkin, pronounces it /tri:/. However, it is pronounced /traɪ/ by other authors. (Wikipedia) PI-SCN-4, ČVUT FIT, Petr Fišer,
7 Trie A tree Nodes have several successors Common prefixes are shared PI-SCN-4, ČVUT FIT, Petr Fišer,
8 Ternary Tree Used for storing of terms (of any kind) Each level associated with one variable given variable ordering Constant depth = number of variables Nodes may have up to 3 successors 0, 1, X Existence of a terminal represents existence of a term 0 X 1 PI-SCN-4, ČVUT FIT, Petr Fišer,
9 Ternary Tree a 0 1 X b c d e a b c d e a b c d b de b de ab ce abe abcde PI-SCN-4, ČVUT FIT, Petr Fišer,
10 Ternary Tree Properties: Insertion of a term in O(n) Looking up a term in O(n) Size: between n (one term) and 3 n+1 (all terms) Truth table: between n (one term) and n.3 n (all terms) Comparison of look-up speeds: Ternary tree n On success On failure < n Truth table n n.p n.p PI-SCN-4, ČVUT FIT, Petr Fišer,
11 Ternary Tree Look-Up Example Searching: ab c d (1001-) a 0 X 1 b failure c d e a b c d e a b c d b de b de ab ce abe abcde PI-SCN-4, ČVUT FIT, Petr Fišer,
12 Ternary Trees References E. Fredkin (1960). "Trie Memory". Communications of the ACM 3 (9): pp T. Sasao, "Ternary Decision Diagrams: Survey, In Proceedings of the 27th International Symposium on Multiple-Valued Logic (ISMVL), 1997, pp S. Hassoun and T. Sasao, Logic Synthesis and Verification", Boston, MA, Kluwer Academic Publishers, 2002, 454 p. P. Fišer and D. Toman, A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms, Proc. of 12th Euromicro Conference on Digital Systems Design (DSD'09), Patras (Greece), , pp PI-SCN-4, ČVUT FIT, Petr Fišer,
13 Boolean Networks - Terminology Boolean (logic) network: directed acyclic (multi)graph Node: a gate (AND, OR, XOR, MUX, buffer, inverter, ) or a primary input/output Generally node has any number of inputs and outputs (?) Signal connection between nodes. Edge in the graph (do not use wire!) Node fan-in: set of nodes connected to the node inputs or the number of node inputs (= number of nodes connected to the node inputs) Node fan-out: set of nodes connected to the node outputs or the number of nodes connected to the node outputs Primary input (PI): node with no fan-in or signals driven by the environment Primary output (PO): node with no fan-out or signals driving the environment PI-SCN-4, ČVUT FIT, Petr Fišer,
14 Boolean Networks - Terminology Transitive fan-in of a node: set of all nodes driving the node, up to PIs Transitive fan-out of a node: set of all nodes driven by the node, up to POs Distance of two nodes: maximum number of signals one needs to pass to reach one node from the other one Level of a node: maximum distance from any of the PIs the level of PIs is 0 Network depth (or network levels ): maximum level Branching: one node output (or PI) feeds two or more nodes (or POs) Reconvergence: there are two or more paths from one node to another PI-SCN-4, ČVUT FIT, Petr Fišer,
15 Random Logic No restriction of node types node implements any function No restriction of the number of node inputs/outputs the most general network description but difficult to manipulate too complex operations big granularity PI-SCN-4, ČVUT FIT, Petr Fišer,
16 Networks Described in BLIF (Berkeley Logic Interchange Format) Each node is a single-output PLA Nodes have one output only Network of single-output nodes implementing any function Used in SIS, MVSIS, ABC G1 G3 G6 G2 G7 G10 G11 G16 G19 PI-SCN-4, ČVUT FIT, Petr Fišer, G22 G23.model C17.inputs G1 G2 G3 G6 G7.outputs G22 G23.names G1 G3 G names G3 G6 G names G11 G2 G names G11 G7 G names G10 G16 G names G16 G19 G end
17 Reduced Boolean Circuits (RBCs) Directed Acyclic Graph (DAG) Primary inputs (variables) are terminals Primary outputs are roots Nodes: Restricted to 2 inputs Operator nodes (AND, OR, XOR, ) Any binary operation Variable nodes terminals Edges can be complemented PI-SCN-4, ČVUT FIT, Petr Fišer,
18 And-Inverter Graphs (AIGs) Directed acyclic graph (DAG) Primary inputs (variables) are terminals Primary outputs are roots Node types restricted to: 2-input AND Inverter (implemented as a complemented edge) Advantages: Universality any network can be simply converted to AIG Scalability no size explosion (like, e.g., in BDDs) Low granularity good for technology mapping High flexibility parts of AIG may be easily restructured Simple operations Implemented in: ABC ( AIGER format ( PI-SCN-4, ČVUT FIT, Petr Fišer,
19 And-Inverter Graphs (AIGs) Example Inverter AND Not canonical PI-SCN-4, ČVUT FIT, Petr Fišer,
20 And-Inverter Graphs (AIGs) Balancing To reduce the depth By application of the associative transform a(bc) = ab(c) Linear time complexity PI-SCN-4, ČVUT FIT, Petr Fišer,
21 And-Inverter Graphs (AIGs) Structural hashing (strashing) Detect isomorphic subgraphs (like in BDDs) Hash table (unique table), AIG manager two nodes having equal fan-ins are merged but canonicity not ensured (only within one logic level) Linear time complexity PI-SCN-4, ČVUT FIT, Petr Fišer,
22 Functionally Reduced AIGs (FRAIGs) BDD, SAT and simulation is used to detect functionally equivalent nodes Ensures functional canonicity of AIG nodes Each node represents a unique function, in terms of PIs (no two nodes in AIG represent the same function) FRAIGs are semi-canonical (one function may have different FRAIGs) PI-SCN-4, ČVUT FIT, Petr Fišer,
23 Structural Choices - Lossless Synthesis Motivation Main disadvantage of standard synthesis processes: strong dependency on the currently processed structure Synthesis is executed in several consecutive steps The processed structure is lost in each synthesis step Sometimes it may be crucial what if I choose a bad synthesis procedure? Everything s lost! What if I want different optimization criteria? Technology mapping resolves this, synthesis steps usually ignore my requirements for the final result Original circuit (BLIF) Synthesis step Optimized circuit (BLIF) Synthesis step Optimized circuit (AIG)... Technology mapping PI-SCN-4, ČVUT FIT, Petr Fišer,
24 Structural Choices - Lossless Synthesis Lossless synthesis Results of all synthesis procedures are put together Technology mapping procedure exploits these choices Original circuit (BLIF) Synthesis step Optimized circuit (BLIF) Synthesis step Optimized circuit (AIG) Choices buffer... Technology mapping PI-SCN-4, ČVUT FIT, Petr Fišer,
25 And-Inverter Graphs (AIGs) Applications: Logic synthesis SAT-solving Technology mapping Formal verification (equivalence checking, model checking) Attempt for a unifying representation in EDA, throughout the whole design-flow PI-SCN-4, ČVUT FIT, Petr Fišer,
26 And-Inverter Graphs (AIGs) References P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification", Proc. ICCAD 04, pp A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06, pp A. Mishchenko and R. Brayton, Scalable logic synthesis using a simple circuit structure, Proc. IWLS 06. A. Mishchenko, S. Chatterjee, R. Jiang, and R. Brayton, FRAIGs: A unifying representation for logic synthesis and verification, ERL Technical Report, EECS Dept., U. C. Berkeley, March S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, Reducing structural bias in technology mapping, Proc. ICCAD '05, pp A. Mishchenko, S. Chatterjee, and R. Brayton, Improvements to technology mapping for LUT-based FPGAs, Proc. FPGA 06, pp PI-SCN-4, ČVUT FIT, Petr Fišer,
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