-COMPUTER ARCillTECTURE. Time : Three hours. -Maximum Marks : 100. AU parts of a question (a, b, etc.) should be answered at one place.

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1 S'09 : 6 FN : CP 406 ( 1451) -COMPUTER ARCillTECTURE Time : Three hours -Maximum Marks : 100 A!Jswer FIVE questions, taking ANY TWO from Group A, _ANY TWO from Group B and ALL from. Group C. - AU parts of a question (a, b, etc.) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches, Unnecessary long answer may result in Joss of marks. Any missing or wrong data may be assumed suitably giving proper justification. Figures on the right-hand side margin indicate full marks. Group A 1. (a) What' is meant by the 'stored-program' concept'? Draw a diagram of von Neumann architecture and explain it briefly. 6 (b) What is meant by 'addressing modes''? Explain any four such modes with suitable examples. (c) Define the terms ~stack' and 'subroutine'. How are they useful in implementation of an architecture of a processor? 8 6 (Tum Over)- AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , ,

2 2. (a) What are the advantages of microprogramming fo design the control unit of a digital computer ~ Explain microprogrammed control organization. 7 (b) Explain the advantages of bit-slice processors over a conventional ALU '? illustrate a bit sliced processor using a suitable schematic diagram. How many 16-bit _ ALU slices can be used for designing a 64-bit ALU? 7 ( c) What is meant by nano programming? How can a given set of nano instructions be generated from a micro instruction? 6 {b) A cache has 64 KByte capacity, 128 byte blocks, and is 4-way sd associative. The system containing the cache uses 32-bit addresses: (i) How many blocks and sets does cache have'? {ii) What is the size of the tag field in bits '? (iii) What is the size of the offset field in bits '? ( iv) What is the size of the index field in bits? Using a schematic diagram, show which parts of the address serve as offset, index, and tag fields. 10 GroupB 3. (a) What is meant by memory hierarchy? Explain with 5. (a) Differentiate between CISC and RISC architectures. a neat diagram. A memory system contains a cache, What are their typical characteristics? Give some a main memory, and a virtual memory. The access time of cache is 5ns and it has an 80% hit ratio. The access time of main memory is loons with a 99 5% hit ratio. The access time of virtual memory is 10 ms. examples(s) of processors of each category. (b) What is meant by 'parallel processing'? Briefly explain Flynn's classification of parallel computers. 6 6 What is the average access time of the hierarchy? 10 (b) What do you understand by 'interleaved memory' '? What are its advantages? What is the bandwidth of a memory system with a latency of 40 ns that transfers 1 byte per operation and is pipelined to allow 4 operations to overlap execution. Assume no pipeline overhead? (a ) With reference to cache memory, defme following terms: (i) Line length, (ii) associativity, (iii) write back, and (iv) write through. 10 (c) In the context of pipeline, what is meant by a 'task' '? Consider a four segment pipeline, draw the diagram in space-time domain for this pipeline, and derive a formula for speed up. For a 4-stage pipeline, the time to perform.a suboperation in each segment is 20 ns for executing 100 tasks. What is the speed-up ratio? 8 6. (a ) What is meant by associative memory'? Explain _ briefly the hardware organisation of such a memory. 6 ( b ) Which are the three major difficulties that cause the instruction pipeline to qeviate from its nom1al operation? 6 S '09: 6FN :CP406(1451) ( 2 ) (Continued) S '09: 6FN: CP406 (1451) { 3 ) (Tum Ove.-) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , ,

3 (c) With reference to multiprocessors system, explain following terms : U) Tightly coupled, (ii) loosely coupled, (m) multiport memory. Enumerate the benefits of a multiprocessors organization. 8 7 (a ) What is an interconnection network? Explain briefly the hypercube inter-connection. 8 ( b ) Define array processing and explain the operations of a SIMD array processor. 6 (c) Explain a crossbar switch. Compare its advantages over a hypercube network (a ) What is a vector pipeline? Explain your answer using a suitable schematic diagram. 6 ( b ) What is asynchronous serial transfer? Illustrate with a 10 bit example. 6 ( c ) How does DMA work? Explain the terms : ( i) bus request, ( ii) bus grant, (iii) burst transfer, and (iv) cycle stealing. 8 ~ Groupe 9. Choose the most appropriate following: answer for the 10x2 ( i) The address space of a 16 bit processor with 2 byte word size would be (a) 512 Kbytes (.b) 256 Kbytes (c) lmbytes (d) 128 bytes ( ii) For performing the instruction execution, the OPCODE should be in which of the following register? (a) MAR (b) IR (c) MBR (d) PC (iii) Computer memory is organized into hierarchy. As one goes down the hierarchy, one finds. (a ) increasing cost/bit. (b) decreasing cost/bit. (c) increasing capacity. ( d ) decreasing capacity. ( iv). Which one of the following semiconductor memory is used for design of cache memory? (a) SRAM (b) Flash (c) DRAM (d) EPROM ( v) The unit of transfer between cache memory and main memory is (a) Byte (b) Word (c) Block ( d) Cylinder S '09: 6FN:CP406(1451) ( 4 ) (Continued) S '09: 6FN: CP406 (1451) ( 5 ) (Tum Over) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , ,

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8 S'10: 6 FN: CP 406 (1451) COMPUTER ARCHITECTURE Time : Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY "I:WO from Group A, ANY TWO from Group B and ALL from Group C. All parts of a question ( a, b, etc. ) should be answered at one place: Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answers may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification. Figures on the right-hand side margin indicate full marks. Group A 1. (a) What are different addressing modes available f~r a typical architecture? Explain any three with suitable example(s). 8 (b) Why are memories organized in hierarchy? Which are the factors to be considered while selecting a particular memory type? Draw a suitable diagram and explain briefly. 6 (c) A memory system contains a cache, main memory and virtual memory. The access time of cache is 10 ns, and it has an 90% hit ratio. The access time of main memory is 100 ns \Yith 99.5% hit ratio. The access time of virtual memory is 10 ms. Calculate the average access-time-of the hierarchy. 6 AMIE(I) STUDY CIRCLE, IInd FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , Web: 8

9 2. (a) What is stack? Why is SP (stack pointer) needed? Using a reverse polish notation trpn). show, with a stack diagram, how the arithmetic expression (6 *8) + (2 *3) will be evaluated. 4+8 (b) What is a subroutine? How are recursive subroutines useful? Explain briefly (a) With reference to control unit of an CPU architecture, explain following terms : (i) Micro- instruction, ( ii) Microprogram, (iii) Pipeline register, (iv) Control memory, (v) Sequencer. 5x2 (b) With reference to RISC architecture, what is meant by 'overlapping register windows'? What is the general relationship among register windows? 10 (c) What is meant by instruction pipeline? Which are the three major difficulties that cause the instruc- tion pipeline to deviate from its normal operation? 4 6. (a) What is content addressable (associative) memory? How is. such a memory implemented.? Explainthe7.'match logic' used for comparison algorithni for two binary numbers. 8 (b) How is bit-slice processor (like AMD 2900) a better alternative for designing control unit of a (b) Differentiate between tightly. coupled and-loosely digital computer? 10 coupled mu~!iprocessors. What are their relative advantages. 4. (a) With reference to cache memory, explain following terms: 3x2 (c) Write a note: on vector and m:tay processing with their representative application areas. 8 (i) Locality of reference (ii) Hit ratio and miss 7. (a) What are the:advantages of using multiprocessing (iii) Mapping. systems? ~at is meant by 'data dependency'? 6 4 (b) Differentiate between 'associative' and 'direct _ mapping' with suitable example(s). 8 (c) Why is direct memory access needed? Explain following terms : {i) Bus request (BR), (ii) Bus grant (BG), (iii) Burst transfer, and (iv) Cycle stealing. 6 Group B 5. (a) Enumerate the characteristic features of RISC and CISC architecture. 6 (b) What are the interconnection networks? Draw a three-dimensional hypercube and explain it. 10 (c) For a 4-stage pipeline, the time required to per.,. form a sub-operation in each: segment is 10 ns for executing lootasks. Calculate the speed up ratio. 4 8~ (a) With reference to pipe lining, what is data hazard? Explain briefly about possible data hazards. 8 (b) What is Amdahl's law? How is incremental improvement in speedup gained? 6 AMIE(I) STUDY CIRCLE, IInd FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , Web: 9

10 (c) What is meant by SIMD computers? Explain the operation of SIMD array processor. Group C 9. Choose the correct I most appropriate answer for the following<: 10 x 2 (i) The memory of a computer system is normally implemented as a hierarchy of three or four levels of semiconductor RAM units with different speeds and sizes. The smallest fast RAM called cache is (a). loosely coupled. (b) tightlycoupled. (c) main merilory. (d) highly coupled. (ii) The unit of transfer of data between cache and main memory, and between cache and CPU are respectively (a) word, block (b) word, word (c) block, word (d) block, block. (iii) Interrupts are provided primarily as a way to improve (a) timing. (b) performance. (c) avoid clashes. (d) efficiency. - 6 (iv) The CPU exchanges the data with memory. Which one of the Nlllowing register specifies the address in memory for next read or write? (a) MAR (b) MBR (c) 110 AR (d) 110 BR (v) The operating system controls the execution of programs on a CPU and manages resources. The most important function of the OS is (a) manage memory. (b) 110 management. (c) buffering. (d) scheduling of processes. (vi) Which one of the following Intel processor does not include on-chip cache memory? (a) (b) (c) (d) Pentium P4 (vii) The major functions or requirements for an 110 module fall into which of following categories : (a) Control and timing (b) Data buffering and error detection (c) Process and data communication (d) All ofthe above. AMIE(I) STUDY CIRCLE, IInd FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , Web: 10

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12 W'10: 6 FN: CP 406(1451).. COMPUTER ARCIDTECfURE Time : Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY TWO from Group A, ANY TWO from Group B and AlL from Group C. AU parts of a question (a, b, etc.) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answers may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification. Figures on the right-hand side margin indicate fuu marks. Group A 1. (a ) Explain the organisation of stack in detail. 6 ( b ) Explain how the conditional branching is implemented in the control unit with a neat block schematic. 6 (c) Give the block diagram of a typical RAM chip. Discuss how the Read and Write operations are performedinaramchip,givingthefunctiontable (a) Explain the one hot method for designing hardware. 10 (b) Discuss on the design of micro-programmed control unit organisation in detail. 6 (c) Write a short note on nano programming (a) With a neat block schematic, explain the design of a microprogrammed control unit. 6 AMIE(I) STUDY CIRCLE, IInd FLOOR, SULTAN TOWER, ROORKEE (UTTARANCHAL) pcourses@hotmail.com Ph: (01332) , Web: 12

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14 S' 11 : 6 FN : CP 406 ( 1451 l COMPUTER ARCHITECTURE Time : Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY TWO finm Group A, ANY TWO from Group B and ALL from Group C. All parts of a question ( a, b, etc. ) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answers may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification Figures on the right-hand side margin indicate full marks. Group A 1. (a) Write a short note on the stack organisation. (b) What do you mean by instruction format? Explain with an example. (c) Discuss two different types of addressing modes with examples of their usage. 2. (a) Explain the relative advantages of a hardwared and a microprogrammed control unit (b) Explain single bus and two bus organisation of a processor using a suitable block diagram. 12 (Turn Over) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 14

15 3. (a) Explain the importance of each type of memory with a diagram of memory hierarchy. 10 (b) Explain the process of virtual to physical address translation with a neat diagram (a) Define an interrupt. Explain the steps through which a processor handles an interrupt. (b) Discuss DMA transfer with a suitable block diagram. (c) Differentiate between synchronous and asynchronous communication. Group B 5. (a) Explain the working of associative memory with a neat diagram. (b) Explain how pipelining is implemented in superscalar processor (c) A non-pipeline system takes 60 ns to process a task. The same task can be processed in sixsegment pipeline with a clock cycle of 10 ns. Determine the speed up ratio of pipeline for 100 tasks. What is the maximum speed up that can be achieved? 8. (a) Consider a program of 15,000 instructions executed by a linear pipeline processor with a clock rate of 25 MHz. Instruction pipeline has five stages and one instruction is issued per clock cycle. Calculate speed-up ratio, efficiency and throughput of this pipelined processor. (b) Point out the advantages and disadvantages of direct mapping and fully associative mapping between cache and main memory. (c) What are multiprocessors? Explain using a block diagram. Group C (c) Differentiate between CISC and RISC processors. Give an example for each processor. 6. (a) Discuss Flynn's classification of computer architectures with diagrams Answer the following in brief: 10 X 2 (i) Define miss penalty. (ii) What is a circular buffer? (b) What are different pipeline hazards? Explain each pipeline hazard. 10 (iii) If clock rate is 150 MHz, what is the cycle time? 7. (a) Briefly discuss the cube interconnection networks. 5 (b) Define the following terms : (i) Throughput rate, (ii) MFLOPS, (iii) Average CPI, (iv) Scalability. 4 x 2 (iv) (v) Differentiate between processor and coprocessor. What is Bit-0 Ring technique? AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 15

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17 W'11 :6 FN:CP 406 (1451) COMPUTER ARCHITECTURE Time: Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY TWO from Group A, ANY Two from Group Band ALL from Group C. All parts of a question ( a, b, etc. ) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answers may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification Figures on the right-hand side margin indicate full marks. Group A l. (a) Suppose a computer supports fixed sized ( 16 bit) two operand instructions. Only regi~ter operands are supported, and two addressing modes are supported. There are 16 registers. What is the maximum number of instructions that the computer can support? 5 (b) What do you understand by addressing mode of an operand? What is the difference between relative and absolute addressing? Explain use of each mode using examples. 1 0 AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 17

18 (c) What is the difference between accumulator architecture and general purpose register architecture? Group B Why is general purpose register architecture 5. (a) Briefly explain why RISC processors are expected considered advantageous? 5 to achieve higher thoughput compared to CISC 2. (a) What is. a control unit in a processor? What is its processors of comparable circuit complexity. 5 role during instruction execution? 5 (b) What do you understand by 'hazard' in a pipelined processor? What are the different types of (b) What is the difference between a hardwared control hazards? How are the different types of hazards unit and a microprogrammed control unit? Explain overcome? the relative advantages of each (c) Distinguish between a instruction pipeline and an (c) Wh~t do you mean by emulation? How is it arithmetic pipeline? 5 useful? 5 6. (a) What is an associative memory? How can 3. (a) Explain the terms TLB and page table. How do associative memory be realized? 8 these help realize a virtual memory system? 10 (b) Compare the relative advantages of the SIMD and (b) What do you understand by Memory Management MIMD architectures. 1 Unit (MMU)? What is its role? 5 (c) Between SIMD and MIMD computers, which (c) Define the teim 'memory access time'. Why is the would be easier to program? Explain your answer. 5 memory access time of cache memory considerably smaller than that for main memory? 5 7. (a) What is an interconnection network? What is its use? 5 4. (a) Explain the operation of DMA using a block diagram. Give an example application ofdma data (b) What is the difference between a single-stage and transfer. 10 multistage interconnection network? Give one example of each. What are the relative advantages (b) What is the difference between a synchronous bus of these two categories of interconnection and an asynchronous bus? What are their relative networks? 10 advantages? 5 (c) Compare the relative advantages of the crossbar (c) Explain how the conflict that arises when two units and hypercube networks. 5 of a computer simultaneously try to transfer data on a bus is resolved (a) Explain at least two applications of associative memory. 10 AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 18

19 (b) What would be the maximum speed up that can be expected while executing I 0 instructions on a 5-stage instruction pipeline? Explain your answer. 5 (c) What is the difference between a linear and nonlinear pipline? What are their relative advantages? 5 Group C 9. Choose the correct answer for the following : 10 X 2 (i) Which one of the following registers is used to keep track of the address ofthe next instruction to execute? (a) Memory data register (b) Memory address register (c) Program counter.. (d) Instruction register (ii) Cache memory enhances (a) memorycapacity. (b) memory access time. (c) secondary storage capacity. (d) secondary storage access time. (iii) Whic one of the following is not a part of a processor? (a) ALU (b) cu (c) Registers (d) System bus (iv)a 32 bit address bus allows access to a memory of capacity (a) 64Mb (b) 16Mb (c) 1Gb (d) 4Gb ( v) CISC machines usually (a) have fewer instruction types than RISC mac nines. (b) use more RAM than ruse machines. (c) have more number of registers than ruse machines. (d) have variable sized instructions, whereas ruse machines have fixed sized instructions. (vi) Pipelining improves CPU perfonnance due to (a) reduced memory access times. (b) increasedmemory. (c) introduction of parallelism (d). use of additional functional units. (vii) The system bus is made up of (a) data bus. (b) data bus and address bus. (c) data bus, address bus, and control bus. (d) data bus, address bus, control bus and commartdbus. (viii) A 5-stage pipeline, with different stages taking 1,3, 1,2, 1 unitsoftime,wouldhaveathroughput of (a) 113 (b) 1/8 (c) 8 (d) 3 W'll: 6 FN :CP 406 ( 1451) ( 4 ) ( C'ontinued) W'll :6FN :CP406(145ll ( 5 ) (Turn Over) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 19

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21 5'12:6 FN:CP 406 (1451) COMPUTER ARCIDTECTURE Tzme : Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY TWO from Group A, ANY TWO from Group Band ALL from Group C. All parts of a question ( a, b, etc. ) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answer may result in loss of marks. Any missing or wrong data may be assumed suitably giving proper justification Figures on the right-hand side margin indicate full marks. Group A 1. (a) What is the difference between a direct and an indirect addressing mode of an operand? How many references to memory are needed for each addressing mode to bring an operand into a processor register? 8 (b) A computer uses a memory unit with 256 K words of32 bits each. Each instruction is stored in one word of memory. Each instruction has two operands- one register direct and one memory direct operand. The instruction has three parts : An operation code, a register code part to specify one of 64 registers, and an address part. (Turn Over) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 21

22 (i) How many bits are there in the instruction <lperation code, the register code part, and the address part? 6 (ii) Draw the instruction word format and indicate the number ofbits in each part (a) What is meant by a hardwired implementation of a control unit? Explain briefly. 7 (b) What is the difference between a synchronous and an asynchronous bus? Discuss their relative advantages. 6 (c) Microprogrammed control is not suitable for RISC architecture. Justify the validity or otherwise of this statement (a) What do you understand by content addressable memory? Explain one example application of content addressable memory. 10 (b) The access time of a cache memory is 100 ns and that of main memory 1000 ns. It is estimated that 80 percent of the memory requests are for read and the remaining 20 percent for write. The hit ratio for read accesses only is 0.9. A write through procedure is used. (i) What is the average access time of the system considering only memory read cycles? 3 (ii) What is the average access time of the system for read and write requests? 3 (iii) What is the hit ratio taking into consideration the write cycle? 4 S'12:6FN:CP406 (1451) ( 2 ) (Continued) 4. (a) What is the difference between isolated 110 and memory-mapped J/0? What are the advantages and disadvantages of each? 10 (b) What is DMA? Explain one practical example ofdma. Why does DMA have priority over the CPU when both request a memory transfer. 10 GroupB 5. (a) Determine the number of clock cycles that it takes to complete execution of 100 instructions in a six segment pipelines. Use this to determine speed up over anon-pipelined processor. 10 (b) Explain the differences between RISC and CISC architectures with examples {a) Explain loosely coupled and tightly-coupled microprocessors, and discuss their relative advantages. 10 (b) What do you mean by hazard in a pipeline? What are the different types of hazards? How can these be overcome? (a) Construct a diagram for a 4 x 4 omega switching network. Show the switch setting required to connect input 3 to output (b) What is the cache coherence problem in a multiprocessor? How can the problem be resolved? Briefly explain the important schemes available for this (a) What is a vector computer? Name two applications that can efficiently be executed on a vector computer. 5 S'l2: 6 FN: CP 406 (1451) ( 3 ) (Turn Over) AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 22

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24 W'13: 6 FN: CP 406 (1451) COMPUTER ARCillTECfURE Time : Three hours Maximum Marks : 100 Answer FIVE questions, taking ANY TWO.from Group A, ANY TWO.from Group Band ALL from Group C. All parts of a question (a, b, etc. ) should be answered at one place. Answer should be brief and to-the-point and be supplemented with neat sketches. Unnecessary long answer may result in loss of marks. Any missing or wrong data may be assumed suitably - giving proper justification. Figures on the right-hand side margin indicate full marks. Group A 1. (a) Explain various mechanisms of data transfer from a peripheral device. 10 (b) What is the difference between a direct and indirect addressing modes? How many references to memory are needed for each type of addressing to bring the operand into a processor register? Briefly explain your answer (a) What is DMA? Explain DMA mode of data transfer using a suitable block diagram. Give an example where DMA mode of data transfer is useful. lo (b) Explain the fetch cycle of instruction execution with respect to the various micro-operations carried out by using a labelled block diagram of the CPU. 10 AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 24

25 3. (a) The acces~ time of a cache memory is 100 ns and that of mam memory 1000 ns. It is estimated that (b) Explain four possible hardware schemes that can be 80% of the memory requests are for read and the used in an inslruction pipeline in order to minimize the remaining 20% for Write. The hit ratio for read access performance. degradation caused by instruction branchonly is 0.9. A write-through procedure is used mg (z) What is the average access time of the system (c) A weather forecasting computation requires 250 considering only memory read cycles? billion floating point operations. The problem is processed ina supercomputer that can perform I 00 mega (iz) What is the average access time of the system for flops. How long will it take to do these calculations? 5 both read and write requests?. 6. (a) What is an associative memory? With the help of a (iiz) What is the hit ratio taking into consideration the suitable block diagram~ explain how it can be write cycles? impk:uiented. 7 (c) Describe in brief the architecture of a vector proces- sor. What are some of the key limitations of this architecture? 8 (b) Explain the concept of a memory hierarchy. Explain the concept of locality of reference and state its importance to the satisfaction operation in presence of hierarchies (a) Define a stack. How can it be implemented? Give one example use of stack. 5 (b) Describe in briefflynn's classification of computer system architecture (a) What do you mean by instruction level parallelism? (b) What is the difference between a microprocessor and a microprogram? Is it possible to design a micro- processor without a microprogram? 5 Write the important approaches available to exploit instruction 1e\'cl parallelism. 5 (b) Construct a schematic blockdiagmm fora4 x 4 omega (c) What is the difference between an 110 mapped 110 switching network. Show the switch setting required and memory mapped 110? What are their advan- to connect input 3 to output I. 5 tages and disadvantages? 5 (c) What is a SIMD computer? Discuss one example (d) What is the difference between an asynchronous and application of this computer. 5 synchronous bus? What are their relative advantages? Are 110 buses synchronous buses? 5 (d) What is a multiprocessor? Briefly discuss its architecture. 5 Group B 5. (a) Discuss the relative advantages of CISC processors and RISC processors (a) Discuss the difference between tightly-coupled and a loosely-coupled computer :from the view point of hardware organisation and programming techniques. Identify the important characteristics of a problem AMIE(I) STUDY CIRCLE, SECOND FLOOR, SULTAN TOWER, ROORKEE (UTTARAKHAND) pcourses@hotmail.com Ph: (01332) Web: 25

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