The Metaport. A Technique for Managing g Code Complexity. Jack Donovan HighIP Design Company

Transcription

1 The Metaport A Technique for Managing g Code Complexity Jack Donovan HighIP Design Company jackd@highipdesign.com

2 Outline Context, Motivation, and Definition Overview of An Example Example Code Snippets Further Investigation

3 Past Techniques SystemC ports sc_port<if> SystemC exports sc_export<if> TLM sockets tlm_target_socket<buswidth> tlm_initiator_socket<buswidth>

4 Problem1: Large Interface Pin Counts Even More signals than shown Some signals are unique per Master or Slave (Initiator or Target) and context dependant Mn_request -> M0_request M7_request

5 Problem2: Complex Simulation Scenarios RTL IP #5 uprocessor IP IP #7 IP #6 Interconnect IP IP #8 AT TLM with Behavioral Functionality IP #1 IP #2 IP #3 IP #4 PCA Interface with PCA Interface with Behavioral Functionality

6 Problem 3: IP Vendor Productivity it Issues Easily swap interfaces to meet customer requirements Never can pick the correct interface Each customer requires a different bus interface Some customers want multiple interfaces OPB vs. PLB as an example Standard d approach to facilitate t productivity it code templates Derive TLM model from High Level Synthesis model Verify once, reuse many Hide details from users that don t care

7 Metaport Use of C++ templates and OOP techniques to implement communication interfaces at different levels of abstraction as needed by the modeling/simulation scenario TLM vs. PCA vs. RTL vs. HW Accelerator vs AHB vs. AXI vs.plb vs. OPB vs Ease in manipulation of ports/exports/etc.

8 Outline Context, Motivation, and Definition Overview of An Example Example Code Snippets Further Investigation

9 Use of Metaports Initiator I MP PLB_P2P T MP Target done_interrupt_sig SYS_plbClk Clock

10 Metaport Initiator Example highip_plb_initiator_mp<pin, plb initiator BUSWIDTH, bus specific params > SYS_plbClk write( address, data, BE, ) read( address, data, BE,.) write_ line( address, *data,..) read_line( address, *data, ) write_burst( address, *data,...) read_burst( address, *data, ) tlm_write( gp ) tlm_read(gp) Initiator Memory API PLB Initiator Metaport Initiator Bus API PLB_PAValid Sl_addrAck PLB_wrDBus<BUSWIDTH> Sl_rdDBus<BUSWIDTH> bind() ()

11 Metaport Initiator Example highip_plb_initiator_mp<tlm, plb initiator BUSWIDTH, bus specific params > write( address, data, BE, ) read( address, data, BE,.) write_line( address, *data,..) Initiator Memory API read_line( address, *data, ) PLB write_burst( address, *data,...) read_burst( address, *data, ) tlm_write( gp ) tlm_read(gp) Initiator Metaport Initiator Bus API initiator_socket bind() ()

12 Use of Initiator Metaport Initiator_Clk Done_interrupt Master Processing Dual Clock Buffer Master cthread Mem API PLB Init MP PLB_signals M_signals SYS_plbClk

13 Target Metaport Example highip_plb_target_mp<pin, plb BUSWIDTH, bus specific params > SYS_plbClk PLB_PAValid PLB_addrAck Target Mem API get( address, data, BE) put( address, data, BE) reset() Memory MetaPort PLB Target Metaport MwrDBus<BUSWIDTH> M_wrDBus<BUSWIDTH> PLB_rdDBus<BUSWIDTH> Target Bus API bind() ()

14 Use of Target Metaport PLB_signals Sl_ signals PLB Target MP decode Mem API Mem API Data Mem CSR Mem API Mem API Target cthread Asynch In API Asynch Out API Asynch Comm MP Asynch Comm MP SYS_plbClk Done_interrupt Application Specific

15 Bringing It All Together Interconnect Initiator I MP T MP Target done_interrupt_sig SYS_plbClk Clock

16 Outline Context, Motivation, and Definition Overview of An Example Example Code Snippets Further Investigation

17 Template Parameters Abstraction PIN TLM Futures TB Test bench mode TLM AT TLM LT TLM PLB extensions PIN & TLM Implementation MEMORY_TYPE BUS_WIDTH PIN Implementation EXTERNAL_BUS_WIDTH NUM_MASTERSMASTERS SMALLEST_MASTER SMALLEST_SLAVE MASTERID WIDTH MASTERID_WIDTH PIN futures FULL_FEATURE_SET

18 Initiator MP Inheritance reporting target_ports<bus_width,.> sc_module target_base<level, MEMORY_TYPE, > plb_target_mp<level, MEMORY_TYPE,..>

19 MetaPort to Interface Binding

20 Instantiation of Interfaces Routing and Arbitration Method

21 50+ PLB exports And signals

22 50+ PLB ports

23 bind() function 50+ PLB ports

24 Indicates PIN Specific Implementation

25 Technique for Template Specialization i Creates a very simple unique struct/class type (user defined type) Enables Template Specialization and readable code

26 Further Investigation Coussy, Philippe; Maraviec, Adam. (2008) High-Level Synthesis: From Algorithm to Digital Circuit, Springer Meyers, Scott. (2005) Effective C++ [3 rd Ed.]. Addison- Wesley Vandevoorde, David; Josuttis, Nicolai M. (2003) C++ Templates: The Complete Guide, Addison-Wesley