Motorola Wafer Level Burn-in and Test

Transcription

1 Motorola Wafer Level Burn-in and Test 00 Southwest Test Workshop Teresa McKenzie, Wafer Level Burn In Engineer Motorola 6501 William Cannon Drive West; Austin, Texas 78735; Page 1

2 Agenda / Outline Motorola Wafer Level Burn In and Test - Direct Contact - Sacrificial Metal Sacrificial Metal Wafer Level Burn-in and Test Methodology History of Sacrificial Metal Wafer Level Burn-in and Test Challenges (Resolved and Present) Page

3 Direct Contact Key Milestones -Qualified process for C4-FCCBGA for PowerPC June 001 product (using Goremate) -Demonstrated test capability for NCSG DSP March 00 product and TSPG 3bit MCU -Working to qualify multi-use Goremate replacement August 00 -Working to qualify 10um pitch Al wirebond August 00 full wafer contactor -Entering product qualification phase for NSCG August 00 DSP product and TSPG 3bit MCU -Working to qualify FC contact on eutectic, high Pb, End of 00 and no PB electroplate PBGA packages Page 3

4 TEL WLBT system installed in Motorola s Final Manufacturing Factory in Austin Page 4

5 Current Package Flow Target WLBT Flow Wafer Fab Bump Sort#1 Unit Probe Memory Repair Post Repair Unit Probe Package Assembly Pre-BI Test Package BI Wafer Fab Bump WLBT Memory Repair Unit Probe Package Assembly Final Test Post-BI Test Standard and WLBT Manufacturing flow for Power PC Devices Page 5

6 CTE matched core multi-layer laminate Inferno TM IC Board wafer vacuum chuck contact pad GoreMateII TM through plated conductor array (Cu / Ni / Au) expanded polytetrafluoroethylene (eptfe) substrate Components of a Full Wafer Contact Solution for Bumped Die Products Page 6

7 WLBT PROCESS OVERVIEW vacuum Align & Assemble Probe and Wafer Load Probe+Wafer Assembly into Test / Burn-in Chamber Burn-in/Test Chambers WLBT Power/Test Module Assembled WLBT Probe & Wafer WLBT Probe & Wafer Assembly Execute Test / Burn-in Program Aligner Unload Probe+Wafer Disassemble Probe and Wafer Loader System Control Module Page 7

8 KGD Sacrificial Metal WLBI - Definitions - Wafer Level Burn-In (WLBI) and Test Parallel, dynamic, excitation of all devices on a wafer to screen for marginal devices for infant mortality by dynamically stressing the integrated circuit at elevated temperature and voltage. Capable of non-volatile memory cycling, module exercising, and testing. Known Good Die (KGD) Die having the same quality and reliability level as that of an equivalent packaged part. Sacrificial Metal (SM) Metal which is temporarily deposited on the wafer to provide electrical signal paths to a die during wafer level burn-in and test. The sacrificial metal is etched away after burn-in and test is complete. Page 8

9 Why the need for WLBI? Smaller form factor requirements in personal communication, computer and automotive markets have increased demand for KGD. Burn-in for KGD at wafer level requires less test insertions and reduces cycle time than with die level burn-in. Similar cycle time reductions can also be realized for wirebond devices by screening out early life failures before assembly. WLBI provides quicker feedback to wafer manufacturing, which improves responsiveness to provide more effective process control. Page 9

10 WLBI Technology Partners The following cooperative effort is currently the only effective WLBI technology in production in the world: Motorola Semiconductor Products Sector Transportation & Standard Products Group (TSPG) Austin, TX» Design and product engineering support for WLBI Strategic Manufacturing Deployment (SMD) Chandler, AZ / Austin, TX» WLBI circuit definition» Production burn-in and data retention bake process» Post-WLBI data processing» WLBI circuit removal» Bump process» Saw, tape and reel MOS 1 Fab Chandler, AZ» Wafer manufacturing» Probe support Delta V Instruments Richardson, TX Design and maintenance of WLBI systems Assembly and repair of WLBI fixtures WLBI software support Page 10

11 Wafer Level Burn-in Methodology Package Burn-in / Die-Level Burn-in Wafer Probe Dicing Sacrificial Metal Wafer Level Burn-in WLBI and Dynamic Test Assembly Carrier Load Wafer Probe (Reduced Time) Test Assembly Dicing Package Burn-in B Carrier Burn-in Test Test Packaged Units KGD Carrier Unload Packaged Units KGD Page 11

12 5 inch Wafer Level Burn-In Methodology M Main Bus Line "Ti-W-Cu" Scribe Grid Structure Cu Mini Polysilicon Bum p Resistor Field Oxide Scribe Grid Edge M Main Bus Line "Ti-W-Cu" M1/M Interconnec t S C R I B E G R I D Resistor in series with pad Cross overs / cross unders for balanced power distribution Bridge pass over die edge oxide moat VSS VDD RECEIVE RESET Contact pogo pads placed at the edge of the wafer CLOCK Page 1

13 5 inch Wafer Level Burn-In Methodology Post wafer fab process (with polyimide) Deposit, pattern and etch sacrificial metal Parallel electrical bussing of all die per quadrant Photo define burn in contact pads Contact current limiting resistors Contact scribe grid cross-unders Burn-In and Data Retention Bake (DRB) test for NVM devices Remove sacrificial metal Die sales, bump or package Page 13

14 8 WLBI Methodology 9 1 B N A N G E C D N 1 N C D N A N 1 N 1 N B N E 1 G B G 1 N A N 1 E C N N 1 E N C D 1 N G B 1 D A N N E C 1 N N 1 B D N A 1 1 G B N D A 1 N G E C 1 N N 1 E B N A 1 E C N N A 1 N G 1 C D N N N G B 1 D N N 1 G B C N N N G E C D A 1 N E N D A 1 1 B N N N 1 B G D A N N E C D A 1 N E N C 1 1 G B N N G N N 1 14 N 1 B N 1 E C D A N N G B C N A 1 N 1 E N D Cluster Arrangement - Viewed Looking at the Wafer Face Page 14

15 8 inch WLBI Methodology Post wafer fab process (with polyimide) Deposit, pattern and etch sacrificial metal Parallel electrical bussing of all die in a cluster Wafer level burn in (6 to 4 15 C) Data Retention Bake ( to 4 70 C) Remove sacrificial metal Bump (flip chip only) Wafer probe Visual, dice, tape and reel Ship to customer Page 15

16 History of Sacrificial Metal Wafer Level Burn-in 5 inch Wafer Program Development began in 199 Eighteen wafer capacity system built in 1994 Production started in 1995 Full lot capacity production system built in 1997 Over million KGD delivered since 1995 with no documented non-volatile memory (NVM) field failures Page 16

17 History of Sacrificial Metal Wafer Level Burn-in 8 inch Wafer Program Single wafer engineering system built in 1997 Successful 8 inch WLBI in 1997 Prototype Production System Built in 1998 Production System Built in 1999 Page 17

18 Resolved Challenges Sacrificial Metal Criteria: Poor sacrificial metal adhesion Good adhesion to polyimide Proper conductivity to carry signals and voltages Ease of sacrificial metal removal after WLBI and test Maintain die pad integrity after sacrificial metal processing Toughness to survive contactor and test conditions Page 18

19 Sacrificial Metal Design: Resolved Challenges S1 S S3 S4 S5 Pow er Ground Burn-in test pad R(die) R(scribe) R(limit) Each die is simulated as a current source to ground Cross-section of node (die) contact This repeats for every die W afer Flat R(die)= total conductor resistance from one die node to the next R(scribe)= total resistance between two main burn-in conductor within sc R(limit)= total resistance of the Current limiting resistor circuit Cluster Scheme Die Scheme Adequate thickness and width to carry the necessary signals and voltages and maintain balanced power distribution. Page 19

20 Polyimide Criteria: Resolved Challenges Blistering sacrificial metal Proper adhesion to sacrificial metal and wafer during test conditions Good definition for adequate step coverage Sufficient cure to survive sacrificial metal processing and test conditions Page 0

21 Resolved Challenges Contactor (Pogo Pin) Criteria: QuickTime and a TIFF decompressor are needed to see this picture. Various pogo pin head shapes Melted Heater Pin Area Custom design spring force, travel distance, head shape, materials Mechanically robust at elevated temperature and 1000s of cycles Ability to integrate the pogo pins into the WLBI fixture Page 1

22 Pogo Block Material Criteria: Resolved Challenges Material A CTE 0 ppm/ºc Material B CTE.5 ppm/ºc Cost Material availability Manufacturability and machinability Durability during WLBI and test at elevated temperature Maintaining planarity and adequate pogo pin compression during WLBI and test Page

23 Resolved Challenges Yield Improvement Through Enhanced System Communication Previous - Recognized Good / Bad Clusters Only - Final Test Results at Probe NC G G G G G G G Current - Recognize Individual Die - Generates Wafer Map Pass / Fail Codes Per Die PE NC G G G G G G G G G G PE G G G G G G G G G PE G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G PE G G G PE G G G G G G G G G PE G G NC PE G G G G G G G G G G G G G G G G G G PE G G G G G G G G G NC NS G G PE G G PE G G G G NC G G G G G G G G G G G PE G G G G G G G G G G G G PE PE G PE G G G G G G G G G G G G G G PE G G NC G G G NC PE G G G G G PE G G G G G G NC G G G NC G G G G G G G G G G G G G G G G G G G G G G G NC G G PE G PE G G G G G G G PE G G G NC G G G NC G G G G G G G PE G G G G G G G NC G G PE G G G G G G PE G NS G G G G G G G G G G G G G G NC G G G G G G G PE G G G G G G G G G G G G G G G PE G G G G G G NC NC G G NC G PE G NS G NC G NC G G G G G G G G G G G G G G G G G G G G G G G G G G G G G PE G G G PE Page 3

24 Present Challenges High Contact Count (HCC) Current HCC # Pogo Pins About 600 About 3000 WLBI Cold Temperature Test (-40 C) Page 4

25 Summary Sacrificial Metal Wafer Level Burn-in and Test Sacrificial metal wafer level burn-in is a low cost test solution to achieving known good die. Motorola has been in production utilizing this technology since Page 5

26 Acknowledgments This speaker would like to acknowledge the teamwork from various Motorola SPS groups, Delta V Instruments, and Despatch Industries that contributed to the development and continuous improvement of this Sacrificial Metal Wafer Level Burn-in and Test program. Page 6

27 Reference Articles W. Ballouli and T. McKenzie, Design For Sacrificial Metal Wafer-Level Burn-In, 001 EtroniX (Advanced Packaging) Conference, February 001 (articles on CDROM). W. Ballouli, T. McKenzie, and N. Alizy, Known Good Die Achieved Through Wafer-Level Burn-In and Test, 6th IEEE/CPMT IEMT Symposium, October 000, pp W. Ballouli, C. Beddingfield, F. Carney, and R. Nair, Wafer- Level KGD Technology for DCA Applications, Advanced Packaging, September 1999, pp T. McKenzie, Wafer Level Burn-in (WLBI) Workshop, Motorola Internal Publication, November 5, W. Ballouli, J. Stroupe, TSM Approach to Wafer Level Burnin, Motorola Internal Publication, Motorola AMT Symposium, January 5, Page 7