ANALOG IP WITH INTELLIGENT IP FROM SYSTEM TO SILICON
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1 ANALOG IP WITH INTELLIGENT IP FROM SYSTEM TO SILICON Torsten Reich, Fraunhofer IIS/EAS IIP
2 Analog IP with Intelligent IP from system to silicon What is Intelligent IP (on silicon level)? Intelligent IP bottom-up: from silicon to system level Intelligent IP top-down: from system level to silicon 2
3 Our VISION Intelligent A/MS IP (IIP) Offering innovative A/MS IP which are flexible as software, processors, memory compilers or soft IP configurable by a wide range of different parameters generated in a few seconds to minutes verified on different technologies in a strictly standardized way 3
4 Intelligent IP A novel approach for analog and mixed-signal IP XFAB 180nm AMS 180nm GF 40nm + testbenches, simulation states + integration model + system behavioral model GF 28nm Silicon available ST 28FDSOI Silicon available GF 22FDX Easy-to-use through Full design data Flexible through Intuitive graphical interface Automatically generated Technology-generic IIP description Seamless design tool integration Can be altered as usual (non-proprietary) Automated configuration 4
5 Intelligent IP Productive application examples & benefits 80MSps 12-bit DAC in STM 28nm FDSOI 500MSps 10-bit DAC in GF 22FDX Intelligent IP based design migration Initial IIP development in 4 weeks (2x speed up) Layout generation: ~10 min (>1.000x speed up) Regeneration (e.g. for 10 bit resolution): ~3 min Design trade-offs by back bias control Silicon available IIP reuse for tech node shrinking (4x speed up) Layout generation: ~5 min (>1.000x speed up) Regeneration for new target: ~ 5 min Design trade-offs by body bias control Silicon available in Q3/2017 5
6 Intelligent IP Use case Configurability for new product requirements Configuration of ADC resolution & Pipeline arrangement 12-bit 10-bit 8-bit Configuration of Sampling rate & Power budget 100 MSps 40 MSps 4 MSps System-level configurability in addition to expert mode input parameters Ready for multiple technology requirements 22nm FDSOI, 28nm FDSOI, 28nm, 40nm, 180nm, for different fabs 6
7 Intelligent IP Flexible to Electrical Requirements Intelligent IP supports electrical requirement flexibility on different levels: Primitive level Design parameter, primitive change, System design automation (ADCs, SMART-Sensor) Functional level Bandwidth, gain, System level INL, ENOB, resolution 7
8 Analog IP with Intelligent IP from system to silicon What is Intelligent IP (on silicon level)? Intelligent IP bottom-up: from silicon to system level Intelligent IP top-down: from system level to silicon 9
9 ADC 1 ADC 2 ADC 3 Intelligent IP bottom-up: from silicon to system System design SystemC, Verilog, Matlab IIP Implementation Transistor-level, behavioral Intelligent IPs (executable, configurable, transistor-level verified) Sub block 1 Sub block 2 Sub block 3 10
10 Analog IP with Intelligent IP from system to silicon What is Intelligent IP (on silicon level)? Intelligent IP bottom-up: from silicon to system level Intelligent IP top-down: from system level to silicon 11
11 ADC 1 ADC 2 ADC 3 Spec 2 Intelligent IP top-down: from system to silicon (1) System design System C library: (configurable) ADC 1 ADC 2 ADC 3 Design Space x1 2 ADC 1 3 ADC 2 IIP ADC 3 Spec 1 Implementation Sub block 1 Sub block 2 Sub block 3 12
12 ADC 1 ADC 2 ADC 3 Spec 2 Intelligent IP top-down: from system to silicon (2) System design System C library: (configurable) ADC 1 ADC 2 ADC 3 Design Space 1 x 2 ADC 1 Re-generation & verification 3 ADC 2 IIP ADC 3 Spec 1 Implementation Sub block 1 Sub block 2 Sub block 3 13
13 ADC 1 ADC 2 Spec 2 Intelligent IP top-down: from system to silicon (3) System design System C library: (configurable) ADC 1 ADC 2 ADC ADC 1 x Design Space New IP design 3 ADC 2 IIP ADC 3 Spec 1 Implementation Sub block 1 Sub block 2 Sub block 3 ReUse of IIPs 14
14 Analog IP with Intelligent IP from system to silicon Conclusion Intelligent IP provides automated design of analog IPs & is in productive use Generation of system models in development Goal: provide configurable SystemC model library in Coside for exiting verified A/MS-IPs A/MS-IPs, which can be re-generated and verified quickly A/MS-IPs, which can be quickly designed using Intelligent IP technology Request: discussion on customer problems and expectations 15
15 INTELLIGENT IP Your Contact IIP Dr. Torsten Reich Fraunhofer IIS/EAS
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