HIGH-SPEED 4K x 8 FourPort TM STATIC RAM

Transcription

1 Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory cells which allow simultaneous access of the same memory locatio Fully asynchronous operation from each of the four ports: P1, P2, P3, and P4 TT-compatible; single 5V (±1%) power supply Available in 128 pin Thin Quad Flatpack package Functional Block Diagram HIGH-PEED 4K x 8 FourPort TM TATIC RAM EAD FINIH (npb) ARE IN EO PROCE - AT TIME BUY EXPIRE JUNE, 18 Industrial temperature range ( 4 C to +85 C) is available for selected speeds Green parts available, see ordering information Description The IDT754 is a high-speed 4K x 8 FourPort tatic RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort tatic RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT754 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT754 provides four independent ports with separate control, R/WP1 CEP1 R/WP4 CEP4 OEP1 OEP4 I/OP1-I/O7P1 COUMN I/O COUMN I/O I/OP4-I/O7P4 AP1 -A11P1 AP2 -A11P2 PORT 1 DECODE OGIC PORT 2 DECODE OGIC MEMORY ARRAY PORT 4 DECODE OGIC PORT 3 DECODE OGIC AP4 -A11P4 AP3 -A11P3 I/OP2-I/O7P2 COUMN I/O COUMN I/O I/OP3-I/O7P3 OEP2 OEP3 CEP2 R/WP2 CEP3 R/WP drw 1 18 Integrated Device Technology, Inc. 1 JUY 18 DC 3241/14

2 address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. It is the user s respoibility to eure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using CMO high-performance technology, this FourPort RAM typically operates on only 75mW of power. The IDT754 is packaged in a 128-pin Thin Quad Flatpack (TQFP). Pin Configuration (1,2,3) 1. All VCC pi must be connected to the power supply. 2. All GND pi must be connected to the ground supply. 3. Package body is approximately 14mm x mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking

3 Pin Configuratio (1,2) ymbol Pin Name A P1 - A11 P1 Address ines - Port 1 A P2 - A11 P2 Address ines - Port 2 A P3 - A11 P3 Address ines - Port 3 A P4 - A11 P4 Address ines - Port 4 I/O P1 - I/O7 P1 Data I/O - Port 1 I/O P2 - I/O7 P2 Data I/O - Port 2 I/O P3 - I/O7 P3 Data I/O - Port 3 Capacitance (1) (TA = + C, f = 1.MHz) TQFP ONY ymbol Parameter Conditio (2) Max. Unit CIN Input Capacitance VIN = V 9 pf COUT Output Capacitance VOUT = V 1 pf 3241 tbl 3 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from V to 3V or from 3V to V. I/O P4 - I/O7 P4 Data I/O - Port 4 R/W P1 Read/Write - Port 1 R/W P2 Read/Write - Port 2 R/W P3 Read/Write - Port 3 R/W P4 Read/Write - Port 4 GND Ground CE P1 Chip Enable - Port 1 CE P2 Chip Enable - Port 2 CE P3 Chip Enable - Port 3 Maximum Operating Temperature and upply Voltage (1) Grade Ambient Temperature GND Vcc Commercial C to +7 C V 5.V + 1% Industrial -4 C to +85 C V 5.V + 1% 1. This is the parameter TA. This is the "itant on" case temperature tbl 4 CE P4 Chip Enable - Port 4 OE P1 Output Enable - Port 1 OE P2 Output Enable - Port 2 OE P3 Output Enable - Port 3 OE P4 Output Enable - Port 4 VCC Power 1. All VCC pi must be connected to the power supply. 2. All GND pi must be connected to the ground supply tbl 1 Absolute Maximum Ratings (1) ymbol Rating Commercial & Industrial Unit Terminal Voltage -.5 to +7. V with Respect to GND VTERM (2) TBIA TTG Temperature Under Bias torage Temperature -55 to +1 o C -65 to + o C IOUT DC Output Current 5 Recommended DC Operating Conditio ymbol Parameter Min. Typ. Max. Unit VCC upply Voltage V GND Ground V VIH Input High Voltage (2) V 3241 tbl 5 1. tresses greater than those listed under ABOUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 1% for more than % of the cycle time or 1 maximum, and is limited to < for the period of VTERM > VCC + 1%. VI Input ow Voltage -.5 (1).8 V 1. VI > -V for pulse width less than VTERM must not exceed Vcc + 1% tbl

4 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,5) (VCC = 5.V ± 1%) 754X 754X Com'l & Ind 754X ymbol Parameter Condition ICC1 ICC2 IB IB1 Operating Power upply Current (All Ports Active) Dynamic Operating Current (All Ports Active) tandby Current (All Ports - TT evel Inputs) Full tandby Current (All Ports - All CMO evel Inputs) CE = VI Outputs Disabled f = (3) CE = VI Outputs Disabled f = fmax (4) COM'. IND. COM'. IND. Version TYP. (2) Max. TYP. (2) Max. TYP. (2) Max. CE = VIH f = fmax (4) COM'. IND. All Ports CE > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = (3) COM'. IND Unit 3241 tbl 6 1. 'X' in part number indicates power rating ( or ). 2. VCC = 5V, TA = + C and are not production tested. 3. f = mea no address or control lines change. 4. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditio of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (VCC = 5.V ± 1%) ymbol Parameter Test Conditio Min. Max. Min. Max. Unit II Input eakage Current (1) VCC = 5.5V, VIN = V to VCC IO Output eakage Current CE = VIH, VOUT = V to VCC 1 5 µa 1 5 µa VO Output ow Voltage IO = V VOH Output High Voltage IOH = V NOTE: 1. At Vcc < 2.V input leakages are undefined tbl

5 AC Test Conditio Input Pulse evels Input Rise/Fall Times Input Timing Reference evels Output Reference evels Output oad GND to 3.V 3 Max. V V Figures 1 and tbl 8 5V 5V 893Ω 893Ω DATAOUT DATAOUT 347Ω 3pF 347Ω 5pF* 3241 drw 4, Figure 1. AC Output Test oad Figure 2. Output Test oad (for tz, thz, twz, tow) *Including scope and jig Timing Waveform of Read Cycle No. 1, Any Port (1) trc toh taa toh DATAOUT PREVIOU DATA VAID DATA VAID NOTE: 1. R/W = VIH, OE = VI, and CE = VI drw

6 AC Electrical Characteristics Over the Operating Temperature and upply Voltage (3) 754X 754X Com'l & Ind 754X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCE trc Read Cycle Time taa Address Access Time tace Chip Enable Access Time taoe Output Enable Access Time 1 toh Output Hold from Address Change tz Output ow-z Time (1,2) thz Output High-Z Time (1,2) 12 tpu Chip Enable to Power Up Time (2) tpd Chip Disable to Power Down Time (2) 1. Traition is measured mv from ow or High-impedance voltage with the Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating ( or ) tbl 9 (1, 2) Timing Waveform of Read Cycle No. 2, Any Port CE tace taoe thz OE tz thz DATAOUT CURRENT ICC IB tpu 5% tz VAID DATA tpd 5% 3241 drw 6 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE traition OW

7 AC Electrical Characteristics Over the Operating Temperature and upply Voltage (5) 754X 754X Com'l & Ind 754X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCE twc Write Cycle Time tew Chip Enable to End-of-Write 3 taw Address Valid to End-of-Write 3 ta Address et-up Time twp Write Pulse Width (3) 3 twr Write Recovery Time tdw Data Valid to End-of-Write thz Output High-Z Time (1,2) tdh Data Hold Time twz Write Enable to Output in High-Z (1,2) 12 tow Output Active from End-of-Write (1,2) twdd Write Pulse to Data Delay (4) tddd Write Data Valid to Read Data Delay (4) tbl 1 1. Traition is measured mv from ow or High-impedance voltage with the Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VI during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. pecified for OE = VIH (refer to Timing Waveform of Write Cycle, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read. 5. 'X' in part number indicates power rating

8 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (5,8) twc OE (6) ta taw (3) twr CE (2) twp (7) thz R/W tz twz (7) tow (7) thz DATAOUT (4) (4) tdw tdh DATAIN 3241 drw 7 Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5) CE twc taw R/W (6) (2) (3) ta tew twr tdw tdh DATAIN 3241 drw 8 1. R/W or CE = VIH during all address traitio. 2. A write occurs during the overlap (tew or twp) of a CE = VI and a R/W = VI. 3. twr is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pi are in the output state, and input signals must not be applied. 5. If the CE OW traition occurs simultaneously with or after the R/W = VI traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Traition is measured mv from ow or High-impedance voltage with the Output Test oad (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VI during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp

9 (1, 2) Timing Waveform of Write with Port-to-Port Read twc ADDR"A" MATCH twp R/W"A" tdw tdh DATAIN"A" VAID ADDR"B" MATCH twdd DATA"B" VAID tddd 1. OE = VI for the reading ports. 2. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port drw 9 Functional Description The IDT754 provides four ports with separate control, address, and I/O pi that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port s OE tur on the output drivers when set OW. READ/ WRITE conditio are illustrated in the table. Table I Read/Write Control Any Port (1) R/W CE OE D-7 Function X H X Z Port Deselected: Power-Down X H X Z CEP1=CEP2=CEP3=CEP4=VIH Power Down Mode IB or IB1 X DATAIN Data on port written into memory (2) H DATAOUT Data in memory output on port X X H Z Outputs Disabled 3241 tbl "H" = VIH, "" = VI, "X" = Don t Care, "Z "= High Impedance 2. For valid write operation, no more than one port can write to the same address location at the same time

10 Ordering Information XXXX Device Type A Power 999 peed A Package A A Process/ Temperature Range A Blank 8 Tube or Tray Tape and Reel Blank I (1) Commercial ( C to +7 C) Industrial (-4 C to +85 C) (2) G Green PRF 128-Pin Thin Quad Plastic Flatpack (PK128) Commercial Only Commercial & Industrial Commercial Only ow Power tandard Power peed in nanoseconds NOTE: 1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. EAD FINIH (npb) parts are in EO process. Product Discontinuation Notice - PDN# P K (4K x 8) FourPort RAM 3241 drw 1 Datasheet Document History 1/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical correctio Added additional notes to pin configuratio 6/4/99: Changed drawing format Page 1 Corrected DC number 9/1/99: Removed Preliminary 11/1/99: Replaced IDT logo 5/23/: Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters changed wording from "open" to "disabled" Changed ±mv to mv in notes 1/22/1: Page 2 & 3 Added date revision for pin configuratio Page 5, 7 & 8 Added Industrial temp to column heading for speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 6 Changed 5 to 3 in AC Test Conditio table Page 1 & 11 Replace TM logo with logo

11 Datasheet Document History (con't) 2//: Page 1 Added green availability to features Page 2 Removed IDT in reference to fabrication Page 2 2V battery backup for ow-power versio are no longer offered Page 2,3 & 1 The package code PK128-1 changed to PK128 to match standard package codes Page 1 Added Tape and Reel and Green to Ordering Information Pages 1-1 Removed all military data including the G18 pin configuration, changed table headings and ordering information to indicate that there is no longer a military offering for this 754 device 7/2/18: Product Discontinuation Notice - PDN# P-17-2 ast time buy expires June, 18 CORPORATE HEADQUARTER for AE: for Tech upport: 624 ilver Creek Valley Road or an Jose, CA fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc