Motivation for Lecture. Market for Memories. Example: FFT Design. Sequential Circuits & D flip-flop. Latches and Registers.

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1 Motivation for Lecture Design Methodologies Storage (registers and memories) Computational platforms Design Methodologies Memories is a crucial part of most designs: What different type of memories are there? How do we implement them? Computational Platforms: What options do we have? What are the trade-offs? Viktor Öwall Design Methodologies: What does a modern digital design environment look like? Cell-phone ASIC complexity and cost! Market for Memories According to a new technical market research report, semiconductor Memory: Technologies and Global Markets, the value of the global semiconductor memory industry was nearly $46.2 billion in 2009, but is expected to increase to nearly $79 billion in 2014, for a 5-year compound annual growth rate (CAGR) of 11.3%. The largest segment of the market, DRAM, or dynamic random access memory, is projected to increase at a CAGR of 10.4% to $41.5 billion in 2014, after being valued at nearly $25.2 billion in NAND, or nonvolatile/nano RAM, which is the second-largest segment of the market, is estimated at $12.8 billion in 2009, and is expected to increase at a 5-year CAGR of 15% to reach more than $25.7 billion in Source: Semiconductor Memory: Technologies and Global Markets, April 2010 From Courtesy: Sven Mattisson, Ericsson Example: FFT Design Report Price: Price:USD $4,850.00!!! Motivation behind the quest for new memory technologies! Sequential Circuits & D flip-flop 8k points FFT for DVB (Digital Video Broadcasting) Properties: can be dynamic or static Latch or Register Latch - level sensitive Register - edge triggered in 0.5mm CMOS Several embedded memories who s properties and size is crucial to the implementation Flip-flop most often refer to an edge triggered register. From Lecture 3. Latches and Registers Dynamic or Static Stored on capacitance Data will change due to leakage. Refresh needed to keep data. Positive Feedback Data is kept as long as power supply is there Figures from Digital IC Design

2 Master Slave Registers Dynamic or Static If a single latch we can get a race when the latch is open We then use a Master-slave register. We have registers, why memories? Static D Flip-flop : 252µm 2 SRAM Memory element : 30µm 2 Flip-flops vs. SRAM Alcatel Microelectronics 0.35µm CMOS technology process Process and library dependent Flip-flops Dual port memory Single port memory Double width memory Flip-flops 1.2 square mm µm CMOS technology process SRAM memory elements The Complete Memory A memory is more than the storage elements, i.e. the memory cells. Address decoders, sense amplifiers, clock buffers, etc Memory array An Overview of Logic Architectures Inside Flash Memory Devices ANDREA SILVAGNI, GIUSEPPE FUSILLO, ROBERTO RAVASIO, MASSIMILIANO PICCA, AND STEFANO ZANARDI PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003 Semiconductor Memory Classification Read-Write Memories (RWM) Random Access SRAM DRAM Register- Bank Non-Random Access FIFO LIFO(Stack) Shiftregister Nonvolatile RWM (NVRWM) PROM EPROM E 2 PROM FLASH Read-Only Memories (Nonvolatile) ROM PLA Nonvolatile = data kept when supply voltage turned off PROM = Programmable rom EPROM = erasable programmable ROM E 2 PROM & Flash= electrically erasable programmable ROM XXPROM & Flash Nonvolatile = data kept when supply voltage turned of PROM = Fuse based a One time programmable EPROM = EEPROM or E 2 PROM = Flash= Usually erasable by UV-light Usually high voltage for programming a removed from circuit when programmed Individual bytes can be erased a slow but versatile Larger than EPROM Larger sections are erased a faster than EEPROM

3 We will now look at some basic implementations ROM FLASH RAM Static Dynamic WL[0] WL[1] WL[2] Pseudo NMOS ROM BL[0] BL[1] BL[2] BL[3] Do we recognize this? WL[3] The placements of transistors decide memory content. A B Pseudo-NMOS Gates V DD Pull up network OUT Pull down network From last lecture: What was the function? A B OUT Properties: + fewer transistors - Static power consumption - Low input not 0 WL[0] WL[1] WL[2] WL[3] Pseudo NMOS NAND ROM BL[0] BL[1] BL[2] on on off on off BL[3] A B Q All transistors ON pulls down Bit Line Non-selected WL =1 WL lines reversed Select WL[2] a WL[0,1,3]=1 and WL[2] = 0 Transistor on selected line shuts off path to WL[0] WL[1] WL[2] WL[3] Pseudo NMOS NOR ROM BL[0] BL[1] BL[2] BL[3] No transitors = always pulled up A B Q One transistor ON pulls down Bit Line NMOS NOR ROM lines overhead Area Reduced by Mirroring WL[0]=0 WL[1]=0 WL[2]=1 WL[3]=0 Pseudo NMOS NOR ROM A B Q One transistor ON pulls down Bit Line NMOS NOR ROM lines overhead Area Reduced by Mirroring Select WL[2] a WL[0,1,3]=0 and WL[2] = 1 NOR or NAND? NOR is faster no series transistors. What is a Flash memory? ROM Read Only Memory NAND is smaller no lines. You can see this if you look at e.g. FLASH memories RAM Random Access Memory FLASH

4 What is a Flash memory? ROM Read Only Memory data doesn t change data remain when powered down RAM Random Access Memory data can be both read and stored data disappears when powered down FLASH data can be both read and stored data remain when powered down Floating Gate Transistor (FAMOS) electrically programmable V TH Floating gate n + n + Control gate Control gate is connected to wordline Floating gate is left unconnected If charged heavily negative a High V TH a No channel If charged removed a Low V TH a Channel WL EPROM, EEPROM and Flash has different ways of controlling the charge of the floating gate BL Flash EEPROM FLASH stucture Control gate erasure Floating gate Thin tunneling oxide word0 word1 n 1 source programming p- substrate n 1 drain word2 word3 Floating gate transistors everywhere! FLASH write, e.g. trap charge Read-Write Memories (RAM) word0 word1 word2 word3 Static (SRAM) Data stored as long as supply is applied Large cells (6 transistors/cell) Fast Dynamic (DRAM) Periodic refresh required Small cells (1-3 transistors/bit) Slower = trapped charge. Transitor is always off a Same content as ROM. Dynamic or Static RAM 6-transistor SRAM Cell WL M2 V dd M4 Q M5 Q M6 M1 M3 1-transistor DRAM BL WL M 1 C S Computational Platforms BL BL C BL Compare dynamic latch/register

5 Processor Programmable Low Design cost CPUs, micro processors, micro controllers, Software vs. Hardware Algorithm Programmble Hardware Reconfigurable hardware No processing Programble Logic Devices (PLD): PLA, PAL, FPGAs, Gate array (include processing), Dedicated Hardware Process chips High Performance Low Power High cost Software or Hardware? Flexibility Performance Requirements Power Consumption Throughput Cost Volume Know how Time to Market Dedicated Hardware Architecture, i.e. you design hardware that makes what you want! Block RAM Virtex from Xilinx BANK 0 BANK 1 PLD, e.g. FPGA Field Programmable Gate Arrays Reconfigurable Fast Turn Around Prototyping Special Purpose Gate Array ASIC Application/Algorithm Specific Integrated Circuit High Calculation Capacity High Utilization Low Power Low Price at Volume Timing BANK 6 BANK 7 BANK 5 BANK 4 BANK 3 BANK 2 IOB Routing Example: Xilinx FPGAs Switching matrix Basic Spartan Architecture Low end FPGA Horizontal Routing Channel Interconnect point Configurable Logic Block Combinational logic Storage elements R Vertical Routing Channel A B/Q 1 /Q 2 C/Q 1 /Q 2 D A B/Q 1 /Q 2 C/Q 1 /Q 2 Any function of up to 4 variables Any function of up to 4 variables D in F G F G F R D Q 1 CE R D Q 2 F D G CE G E Clock CE Xilinx Virtex-II Pro Heterogeneous Programmable Platforms FPGA Fabric From Xilinx: Embedded PowerPc Embedded memories Hardwired multipliers High-speed I/O Courtesy Xilinx

6 Examples of FPGA Development Boards e.g. from Digilent ( Gate Arrays the old way Fabricating with an array of n- and p-transistors and using design-specific metalization in routing channels. Spartan3 Board US$193 (2011) Xilinx Spartan-3 FPGA w/ twelve 18-bit multipliers, 216Kbits of block RAM 2Mbit Platform Flash Serial port, VGA port, and PS/2 mouse/keyboard port 1Mbyte on-board 10ns SRAM etc Virtex-II Pro Board US$1599, (499 academic) (2011) Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, bit multipliers, 2,448Kb of block RAM DDR SDRAM DIMM that can accept up to 2Gbytes of RAM 10/100 Ethernet port, USB2 port, XSGA Video port Audio Codec Compact Flash card slot etc Before metalization After metalization Design Hardware, i.e. ASIC (Application Specific Integrated Circuit) ASIC Synthesis Behavioral or Structural Synthesis Use Cell library Fast Design Process Simplified re-design Semi Custom Full Custom Design for Performance Layout of all cells Highest Calculation Cap. Lowest Power Smallest area Highest Design Cost Design Methodologies Design Methodology, contnd. Design Methodology Three abstractions: Behavioral, structural and geometrical Moving betwen the domains Amount of Automatization increase RTL- Implementation, we specify registers and operations without clocking separately. 32 A Y Y=A*B+C 48 Standard Design Flow of Today B C

7 Design Flow: a simplified view HDL (VHDL/Verilog/...) Simulation Cell library Synthesis P&R VHDL Very High Speed Integrated Circuit (VHSIC) Hardware Description Language A Technology Independent, Standard Hardware description Language (HDL), used for digital system modeling, simulation, and synthesis. Configuration Post-layout sim. Fabrication VHDL was developed as a language for modeling and simulation. Consequence: Mismatch between simulation and synthesis -- Most constructs in VHDL are fine for simulation, but cannot be synthesized, e.g., after, time, etc. With restrictions, VHDL can be used for synthesis. Combinational and Sequential Parts Some small examples of designing with VHDL. You re not expected to learn VHDL but just get an impression what it looks like Process Multiplexer Process Example II Process Example II register with synchrounus reset process (clk, reset) if clk event and clk= 1 then if (Reset = '0') then Q <= '0'; elseif enable= 1 then Q <= D; end process ; Case command Example: Multiplexer architecture behv1 of Mux is process(i3,i2,i1,i0,s) --nested in process -- use case statement case S is when "00" => Op <= I0; --sequential statements when "01" => Op <= I1; when "10" => Op <= I2; when "11" => Op <= I3; when others => Op <= "ZZZ"; -- end case; end process; end behv1; I0 I1 I2 I3 S

8 IF vs. CASE statements If and case statements generate different HW a a b q b q c c c1 c2 c Mux Case statement Case c is when 01 => q <= a; when 10 => q <= b; when others => q <= c; End case; Mux Use case if you have more than 3 inputs Mux If statement If (c1= 1 ) then q <= a; Elseif (c2 = 1 ) then q <= b; Else q <= c; End if; You need to understand the underlying hardware and what the tools do to be able to write good HDL code. The same as for any other program! Basic State Machine Transforming a State Machine into HW St0 St1 St0 St1 Input d Behavioural Logic Combinatonial part Output q A Typical state machine Typical FSM State r D Clock SequenAal part Generic Architecture for FSMs next state rin Realization of FSMs St0 St1 Realization of FSMs- cont d Architecture declaration (combinatonial part) architecture implementation of state_machine is type state_type is (st0, st1,st2, st3); -- defines states; signal state, next_state : state_type; signal next_output STD_LOGIC_VECTOR (1 downto 0); Entity declaration library IEEE;use IEEE.STD_LOGIC_1164.all; entity state_machine is port (clk : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC_VECTOR(1 downto 0); output : out STD_LOGIC_VECTOR(1 downto 0) ); end state_machine; combinatonial : process (input,state,state) case (state) is -- Current state and input dependent when st0 => if (input = 01 ) then next_state <= st1; output <= 01 when... when others => next_state <= next_state; -- Default output <= 00 ; end case; end process; St1 St0 Realization of FSMs- cont d Sequential part: synchronous : process (clk,reset) if clk event and clk = 1 then if reset = 1 then state <= st0; else state <= next_state; end process; end architecture; Input d State St0 St1 Behavioural Logic Combinatonial part D Clock SequenAal part Output q next _state You can learn more in ETIN20 Digital IC-design. and EITF35 Introduction to Structured VLSI Design