EE260: Digital Design, Spring 2018
|
|
- Bernard Wright
- 5 years ago
- Views:
Transcription
1 Topics Verilog Module 1 Introduction Yao Zheng (Based on the slides of Prof. Jim Duckworth) Background to Verilog Introduction to language Programmable Logic Devices CPLDs and FPGAs FPGA architecture Nexys 3 Board (with Spartan 6 FPGA) [discontinued] Basys 3 Board (with Artix-7 FPGA) Nexys4DDR Board (with Artix-7 FPGA) Using Verilog to synthesize and implement a design Verilog overview Hardware Description Languages Example HDL's : ABEL, VERILOG, VHDL Advantages: Documentation Flexibility (easier to make design changes or mods) Portability (if HDL is standard) One language for modeling, simulation (test benches), and synthesis Let synthesis worry about gate generation Engineer productivity However: A different way of approaching design engineers are used to thinking and designing using graphics (schematics) instead of text. Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog enhanced version Verilog-XL 1987: Verilog-XL becoming more popular (same year VHDL released as IEEE standard) 1989: Cadence bought Gateway 1995: Verilog adopted by IEEE as standard 1364 Verilog HDL, Verilog : First major revision (cleanup and enhancements) Standard (or Verilog 2001) System Verilog under development Better system simulation and verification support Books Create Verilog Module FPGA Prototyping by Verilog Examples, 2008, Pong P. Chu, Wiley Starters Guide to Verilog 2001 by Ciletti, 2004, Prentice Hall Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic, 2003, McGraw-Hill, Advanced Digital Design with the Verilog HDL, by Ciletti, 2003, Prentice-Hall, HDL Chip Design by Smith, 1996, Doone Publications, Verilog Styles for Synthesis of Digital Systems by Smith and Franzon, 2000, Prentice Hall, Verilog HDL by Palnitkar, 2003, Prentice Hall, Verilog for Digital Design by Vhadi and Lysecky, 2007, Wiley, Verilog HDL 1: Introduction of FPGA and Verilog 1
2 No separate entity and arch just module Ports can be input, output, or inout Note: Verilog 2001 has alternative port style: (input a, b, sel, output y); Module Created Add assign statement Similar to VHDL conditional signal assignment continuous assignment Same hardware produced as with VHDL Also place in column: ( input a, input b, input sel, output y ); Verilog - general comments VHDL is like ADA and Pascal in style Strongly typed more robust than Verilog In Verilog it is easier to make mistakes Watch for signals of different widths No default required for case statement, etc Verilog is more like the c language Verilog IS case sensitive White space is OK Statements terminated with semicolon (;) Verilog statements between module and endmodule Comments // single line and /* and */ Verilog Four-value logic system 0 logic zero, or false condition 1 logic 1, or true condition x, X unknown logic value z, Z - high-impedance state Number formats b, B binary d, D decimal (default) h, H hexadecimal o, O octal 16 H789A 16-bit number in hex format 1 b0 1-bit Example Synthesis Results (not Xilinx) Verilog Notes There is no explicit reference to actual hardware components There are no D-type flip-flops, mux, etc Required logic is inferred from the Verilog description Same Verilog can target many different devices There are many alternative ways to describe the required behavior of the final system Exactly the same hardware will be produced Some ways are more intuitive and easier to read Remember that the synthesis tools must be able to deduce your intent and system requirements For sequential circuits it is usually necessary to follow recommended templates and style Verilog HDL 1: Introduction of FPGA and Verilog 2
3 Programmable Logic Devices Xilinx user programmable devices FPGAs Field Programmable Gate Array Virtex 4, 5, 6, Kintex-7 Spartan 3, Spartan 6, Artix-7 Consist of configurable logic blocks Provides look-up tables to implement logic Storage devices to implement flip-flops and latches CPLDs Complex Programmable Logic Devices CoolRunner-II CPLDS (1.8 and 3.3 volt devices) XC9500 Series (3.3 and 5 volt devices) Consist of macrocells that contain programmable and-or matrix with flip-flops Altera has a similar range of devices Electronic Components (Xilinx) Source: Dataquest Programmable Logic Devices (PLDs) SPLDs (PALs) Standard Logic Gate Arrays Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. GateArray CPLDs Logic ASIC Cell-Based ICs FPGAs Full Custom ICs Common Resources Configurable Logic Blocks (CLB) Memory Look-Up Table AND-OR planes Simple gates Input / Output Blocks (IOB) Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing Local, internal feedback, and global Xilinx Products (Xilinx) Overview of Xilinx FPGA Architecture (Xilinx) Complex Programmable Logic Device (CPLD) CPLDs and FPGAs Field-Programmable Gate Array (FPGA) Architecture Density Performance PAL/22V10-like More Combinational Low-to-medium K logic gates Predictable timing Up to 250 MHz today Gate array-like More Registers + RAM Medium-to-high 1K to 3.2M system gates Application dependent Up to 200 MHz today Interconnect Crossbar Switch Incremental Spartan-6/Artix-7 FPGA Family Specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. Delivers an optimal balance of low risk, low cost, and low power for cost-sensitive applications Offers advanced power management technology, up to 150K logic cells, PCI express blocks, memory support, DSP slices, and transceivers DSP48A slice contains 18 by 18 multiplier, adder and accumulator Device CLBs slices CLB flip-flops DSP48A slices Block Ram (18 Kb) User IO Price (1 off) XC6LX16 2,278 18, $30 XC7A35T 5,200 41, $39 XC7A100T 15, , $123 Programmable Functional Elements Configurable Logic Blocks (CLBs) RAM-based look-up tables to implement logic Storage elements for flip-flops or latches Input/Output Blocks Supports bidirectional data flow and 3-state operation Supports different signal standards including LVDS Double-data rate registers included Digitally controlled impedance provides on-chip terminations Block RAM provides data storage 18-Kbit dual-port blocks Multiplier blocks (accepts two 18-bit binary numbers) Digital Clock Manager (DCM) Provides distribution, delaying, mult, div, phase shift of clocks Verilog HDL 1: Introduction of FPGA and Verilog 3
4 Slices and CLBs (Xilinx) Simplified Slice Structure (Xilinx) Each Virtex -II CLB contains four slices Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs A switch matrix provides access to general routing resources Switch Matrix COUT COUT BUFT BUFT Slice S3 Slice S2 SHIFT Slice S1 Slice S0 Local Routing Each slice has four outputs Two registered outputs, two non-registered outputs Two BUFTs associated with each CLB, accessible by all 16 CLB outputs Carry logic runs vertically, up only Two independent carry chains per CLB Slice 0 LUT Carry LUT Carry PRE D Q CE CLR D PRE CE Q CIN CIN CLR Detailed Slice Structure (Xilinx) Look-Up Tables (Xilinx) Combinatorial logic is stored in Look-Up Tables (LUTs) Also called Function Generators (FGs) A B C D Z Capacity is limited by number of inputs, not complexity Delay through the LUT is constant A B C D Combinatorial Logic Z Flexible Sequential Elements (Xilinx) IOB Element (Xilinx) Can be flip-flops or latches Two in each slice; eight in each CLB Inputs can come from LUTs or from an independent CLB input Separate set and reset controls Can be synchronous or asynchronous All controls are shared within a slice Control signals can be inverted locally within a slice FDRSE_1 D S Q CE R FDCPE D PRE Q CE CLR LDCPE D PRE Q CE G CLR Input path Two DDR registers Output path Two DDR registers Two 3-state enable DDR registers Separate clocks and clock enables for I and O Set and reset signals are shared Reg DDR MUX OCK1 Reg OCK2 3-state Reg DDR MUX OCK1 Reg OCK2 Output IOB Input Reg ICK1 Reg ICK2 PAD Verilog HDL 1: Introduction of FPGA and Verilog 4
5 SelectIO Standard (Xilinx) Allows direct connections to external signals of varied voltages and thresholds Optimizes the speed/noise tradeoff Saves having to place interface components onto your board Differential signaling standards LVDS, BLVDS, ULVDS LDT LVPECL Single-ended I/O standards LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz) GTL, GTLP and more! Digital Controlled Impedance (DCI) DCI provides Output drivers that match the impedance of the traces On-chip termination for receivers and transmitters DCI advantages Improves signal integrity by eliminating stub reflections Reduces board routing complexity and component count by eliminating external resistors Internal feedback circuit eliminates the effects of temperature, voltage, and process variations Block SelectRAM Resources (Xilinx) Up to 3.5 Mb of RAM in 18-kb blocks Synchronous read and write True dual-port memory Each port has synchronous read and write capability Different clocks for each port Supports initial values Synchronous reset on output latches Supports parity bits One parity bit per eight data bits Dedicated Multiplier Blocks (Xilinx) 18-bit twos complement signed operation Optimized to implement multiply and accumulate functions Multipliers are physically located next to block SelectRAM memory Data_A (18 bits) Data_B (18 bits) 18 x 18 Multiplier Output (36 bits) 4 x 4 signed 8 x 8 signed 12 x 12 signed 18 x 18 signed Nexys3 Board ($139 now $189) Note: The Nexys3 is no longer in production and is not recommended for new installations. When the current stock is depleted, it will be discontinued. Basys 3 Artix-7 Board ($79) Based on latest Artix-7 FPGA (XC7A35T-1CPG236C) Verilog HDL 1: Introduction of FPGA and Verilog 5
6 Nexys 4 DDR Board ($159) Based on latest Artix-7 FPGA (XC7A100T-1CSG324C) Xilinx Design Process (Xilinx) HDL code Step1: Design Two design entry methods: HDL(Verilog or VHDL) or schematic drawings Synthesize Step 2: Synthesize to create Netlist Translates V, VHD, SCH files into an industry standard format EDIF file Step 3: Implement design (netlist) Translate, Map, Place & Route Step 4: Configure FPGA Download BIT file into FPGA Implement Netlist BIT File Schematic Synthesis CONSTRAINTS Implementation CONSTRAINTS Xilinx Design Flow (Xilinx) Program the FPGA (Xilinx) Plan & Budget Implement Translate Map Place & Route Attain Timing Closure Create Code/ Schematic Functional Simulation Timing Simulation HDL RTL Simulation Synthesize to createnetlist Create Bit File There are three ways to program an FPGA Through a PROM device You will need to generate a file that the PROM programmer will understand Directly from the computer Use the impact configuration tool (need JTAG) Use USB connector Digilent Adept tool Decoder Tutorial Demo Example Verilog Source Code sw0 sw1 sw2 led0 led1 led2 led3 led4 led5 led6 led7 Verilog HDL 1: Introduction of FPGA and Verilog 6
7 Synthesizing the Design View the Schematic Representation * HDL Synthesis * Synthesizing Unit <decoder>. Related source file is "C:\ece3829\decoder\decoder.v". Found 8x8-bit Read Only RAM for signal <led> Summary: inferred 1 RAM(s). Unit <decoder> synthesized. Decoder Implemented on FPGA Zooming in on Logic Slice Assigning Package Pins New Implementation to Match Target Verilog HDL 1: Introduction of FPGA and Verilog 7
8 Top-Down Design Hierarchy Instantiate module (counter example with decoder) module decoder( input [3:0] count, output [6:0] seven_seg ); // instantiate decoder module in counter // using position of ports (positional association) decoder d1 (count_val, seven_seg_val); // or using formal and actual names (named association) decoder d1 (.count(count_val),.seven_seg(seven_seg_val)); Verilog and VHDL Reminder VHDL - like Pascal and Ada programming languages Verilog - more like C programming language But remember they are Hardware Description Languages - They are NOT programming languages FPGAs do NOT contain an hidden microprocessor or interpreter or memory that executes the VHDL or Verilog code Synthesis tools prepare a hardware design that is inferred from the behavior described by the HDL A bit stream is transferred to the programmable device to configure the device No shortcuts! Need to understand combinational/sequential logic Uses subset of language for synthesis Check - could you design circuit from description? Verilog logic and numbers Verilog Basic Syntax Four-value logic system 0 logic zero, or false condition 1 logic 1, or true condition x, X unknown logic value z, Z - high-impedance state Number formats b, B binary d, D decimal (default) h, H hexadecimal o, O octal 16 H789A 16-bit number in hex format 1 b0 1-bit Constants parameter parameter parameter Nets wire wire[7:0] Registers reg reg[7:0] Verilog types DIME = 10; width = 32, nickel = 5; quarter = 8 b0010_0101; clock, reset_n; a_bus; clock, reset_n; a_bus; Integer only for use as general purpose variables in loops integer n; Bitwise Operators ~ negation Verilog VHDL & and y = a & b; y = a AND b; inclusive or y = a b; y = A OR b; ^ exclusive or y = a ^ b; y = a XOR b; y = ~(a & b); y = A NAND b; y = ~ a; y = NOT a; Reduction (no direct equivalent in VHDL) Accept single bus and return single bit result & and y = & a_bus; ~& nand or y = a_bus; ^ exclusive or Verilog HDL 1: Introduction of FPGA and Verilog 8
9 Operators (cont d) Relational (return 1 for true, 0 for false) < less than, <= > greater than >= Equality == logical equality!= logical inequality Logical Comparison Operators! logical negation && logical and logical or Arithmetic Operators + - * Shift << >> Operators (cont d) logical shift left, (<<< arithmetic) logical shift right (>>> arithmetic) Conditional Only in Verilog - selects one of pair expressions? : Logical expression before? is evaluated If true, the expression before : is assigned to output If false, expression after : is assigned to output Y = (A > B)? 1 : 0 Y = (A == B)? A + B : A B Simple Combinational Example View Technology Schematic Decoder Tutorial Demo Example Verilog Source Code led0 sw0 sw1 sw2 led1 led2 led3 led4 led5 led6 led7 Verilog HDL 1: Introduction of FPGA and Verilog 9
10 VHDL Process Signal assignments Verilog always statement Concurrent statements Continuous assignment - assign Verilog wire and register data objects Wire net, connects two signals together wire clk, en; wire [15:0] a_bus; Reg register, holds its value from one procedural assignment statement to the next Does not imply a physical register depends on use reg [7:0] b_bus; Index and Slice Internal wires VHDL Use to and downto to specify slice Concatenation & c_bus(3 downto 0) <= b_bus(7 downto 4); c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & 0 ; Verilog Use colon : Concatenation {,} assign c_bus[3:0] = b_bus[7:4]; assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1 b0}; Declare internal wires: VHDL reside in process statement Verilog Sequential Statements reside in an always statement if statements (no endif) case statements (endcase) for, repeat while loop statements 2 to 4 decoder with enable Decoder always statement Combinational logic using always statement with sensitivity list similar to VHDL process for cyclic behavior (@) event control operator begin.. end block statement note reg for y Note: use begin and end to block sequential statements Verilog HDL 1: Introduction of FPGA and Verilog 10
11 Decoder (cont d) Combinational logic using always statement with sensitivity list similar to VHDL process for cyclic behavior event control operator begin.. end block statement Statements execute sequentially if statement Sensitivity list case statement (a or b or c) Note: case expression can concatenate signals ({,}) Verilog 2001 allows comma-separated list (a, b, c) Decoder CASE statement CASE is better for this type of design - no priority Exactly same logic produced Decoder 3 to 8 with CASE MUX example Example multiplexer with conditional operator Selects different values for the target signal priority associated with series of conditions (similar to an IF statement) i0 i1 i2 i3 q a. b. Synthesis Results Technology Schematic Mux with CASE statement Include all inputs on sensitivity list Elaborating module <mux_case>. WARNING:HDLCompiler:91 - "C:\ece3829\mux_case\mux_case.v" Line 34: Signal <i> missing in the sensitivity list is added for synthesis purposes. HDL and postsynthesis simulations may differ as a result. O = ((I0 * I1 * I3) + (!I0 * I1 * I4) + (!I0 *!I1 * I5) + (I0 *!I1 * I2)); Verilog HDL 1: Introduction of FPGA and Verilog 11
12 Mux fixed sensitivity list Exact same logic produced as using conditional operator Priority Encoder Priority Encoder using conditional operator Priority order determined by sequence similar to if-else statement Encoder Technology Schematic Add gs output * HDL Synthesis * Synthesizing Unit <encoder>. Related source file is "C:\ece3829\encoder\encoder.v". WARNING:Xst:647 - Input <i0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: inferred 2 Multiplexer(s). Unit <encoder> synthesized. ============================================== HDL Synthesis Report ================= Macro Statistics # Multiplexers 2-bit 2-to-1 multiplexer : 2 : 2 ============================================== ================= Synthesize - Design Summary Implement Design * Design Summary * Clock Information: No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 0 out of 18,224 0% Number of Slice LUTs: 2 out of 9,112 1% Number used as logic: 2 out of 9,112 1% Number using O6 output only: 1 Number using O5 output only: 0 Number using O5 and O6: 1 Number used as ROM: 0 Number used as Memory: 0 out of 2,176 0% Timing Summary: Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 5.456ns Slice Logic Distribution: Number of occupied Slices: 2 out of 2,278 1% Number of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 2 Number with an unused Flip Flop: 2 out of 2 100% Number with an unused LUT: 0 out of 2 0% Number of fully used LUT-FF pairs: 0 out of 2 0% Number of slice register sites lost to control set restrictions: 0 out of 18,224 0% Verilog HDL 1: Introduction of FPGA and Verilog 12
13 Creating adder using LUTs Technology Schematic No errors or warnings! Example of simple mistake Top-Down Design Hierarchy Instantiate module (counter example with decoder) module decoder( input [3:0] count, output [6:0] seven_seg ); // instantiate decoder module in counter // using position of ports decoder d1 (count_val, seven_seg_val); // or using formal and actual names decoder d1 (.count(count_val),.seven_seg(seven_seg_val)); Tri-state example Using conditional operator in continuous assignment Verilog HDL 1: Introduction of FPGA and Verilog 13
Verilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
More informationVerilog. Verilog for Synthesis
Verilog Verilog for Synthesis 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog enhanced version Verilog-XL 1987: Verilog-XL becoming more popular
More informationBasic FPGA Architecture Xilinx, Inc. All Rights Reserved
Basic FPGA Architecture 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Identify the basic architectural resources of the Virtex -II FPGA List the differences
More informationVerilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered
More informationVirtex-II Architecture
Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) edicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationFPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationFPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed
More informationEE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200
More informationINTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
More informationField Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
More informationField Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
More informationToday. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
More informationIntroduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.
More informationVerilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationEECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
More informationVirtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued)
Virtex-II Architecture SONET / SDH Virtex II technical, Design Solutions PCI-X PCI DCM Distri RAM 18Kb BRAM Multiplier LVDS FIFO Shift Registers BLVDS SDRAM QDR SRAM Backplane Rev 4 March 4th. 2002 J-L
More informationOutline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
More informationA Brief Introduction to Verilog Hardware Definition Language (HDL)
www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital
More informationGraduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE
FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints
More informationComputer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog
Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C
More informationLecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
More informationSummary. Introduction. Application Note: Virtex, Virtex-E, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro. XAPP152 (v2.1) September 17, 2003
Application Note: Virtex, Virtex-E, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro Xilinx Tools: The Estimator XAPP152 (v2.1) September 17, 2003 Summary This application note is offered as complementary
More informationPINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
More informationAbi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More informationHDLs and SystemVerilog. Digital Computer Design
HDLs and SystemVerilog Digital Computer Design Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function
More informationEvolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
More informationBasic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
More informationCSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for
More informationECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
More informationVerilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design
Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is
More informationEEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 8: Short Introduction to Verilog * Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 Overview Recap + Questions? What is a HDL? Why do we
More informationECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
More information! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!
More informationA Verilog Primer. An Overview of Verilog for Digital Design and Simulation
A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,
More informationMemory and Programmable Logic
Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),
More informationCSE140L: Components and Design
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam
More information14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages
14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs
More informationCS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
More informationSpiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
More informationLecture #2: Verilog HDL
Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize
More informationRegister Transfer Level in Verilog: Part I
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationProgrammable Logic. Any other approaches?
Programmable Logic So far, have only talked about PALs (see 22V10 figure next page). What is the next step in the evolution of PLDs? More gates! How do we get more gates? We could put several PALs on one
More informationIntroduction to Verilog/System Verilog
NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationLab 3: Standard Combinational Components
Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level
More informationFPGA architecture and design technology
CE 435 Embedded Systems Spring 2017 FPGA architecture and design technology Nikos Bellas Computer and Communications Engineering Department University of Thessaly 1 FPGA fabric A generic island-style FPGA
More informationThe Xilinx XC6200 chip, the software tools and the board development tools
The Xilinx XC6200 chip, the software tools and the board development tools What is an FPGA? Field Programmable Gate Array Fully programmable alternative to a customized chip Used to implement functions
More informationVHX - Xilinx - FPGA Programming in VHDL
Training Xilinx - FPGA Programming in VHDL: This course explains how to design with VHDL on Xilinx FPGAs using ISE Design Suite - Programming: Logique Programmable VHX - Xilinx - FPGA Programming in VHDL
More informationSynthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1
Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out
More informationIntroduction to Verilog HDL
Introduction to Verilog HDL Ben Abdallah Abderazek National University of Electro-communications, Tokyo, Graduate School of information Systems May 2004 04/09/08 1 What you will understand after having
More informationLogic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis
Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital
More informationEN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages
EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 1 Introduction to Verilog
More informationXilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Introduction to FPGA design Rakesh Gangarajaiah Rakesh.gangarajaiah@eit.lth.se Slides from Chenxin Zhang and Steffan Malkowsky WWW.FPGA What is FPGA? Field
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationEECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationTSEA44 - Design for FPGAs
2015-11-24 Now for something else... Adapting designs to FPGAs Why? Clock frequency Area Power Target FPGA architecture: Xilinx FPGAs with 4 input LUTs (such as Virtex-II) Determining the maximum frequency
More informationBuilding Combinatorial Circuit Using Behavioral Modeling Lab
Building Combinatorial Circuit Using Behavioral Modeling Lab Overview: In this lab you will learn how to model a combinatorial circuit using behavioral modeling style of Verilog HDL. You will model a combinatorial
More informationHardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationNote: Closed book no notes or other material allowed, no calculators or other electronic devices.
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page
More informationC-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly
More informationThe Virtex FPGA and Introduction to design techniques
The Virtex FPGA and Introduction to design techniques SM098 Computation Structures Lecture 6 Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL
More informationHDL Coding Style Xilinx, Inc. All Rights Reserved
HDL Coding Style Objective After completing this module, you will be able to: Select a proper coding style to create efficient FPGA designs Specify Xilinx resources that need to be instantiated for various
More informationLaboratory Memory Components
Laboratory 3 3. Memory Components 3.1 Objectives Design, implement and test Register File Read only Memories ROMs Random Access Memories RAMs Familiarize the students with Xilinx ISE WebPack Xilinx Synthesis
More informationEECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline
EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction
More informationVerilog Design Principles
16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes
More informationLab Manual for COE 203: Digital Design Lab
Lab Manual for COE 203: Digital Design Lab 1 Table of Contents 1. Prototyping of Logic Circuits using Discrete Components...3 2. Prototyping of Logic Circuits using EEPROMs...9 3. Introduction to FPGA
More informationProgrammable Logic Devices
Programmable Logic Devices INTRODUCTION A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD
More informationHardware description languages
Specifying digital circuits Schematics (what we ve done so far) Structural description Describe circuit as interconnected elements Build complex circuits using hierarchy Large circuits are unreadable Hardware
More informationHardware Description Languages: Verilog
Hardware Description Languages: Verilog Verilog Structural Models (Combinational) Behavioral Models Syntax Examples CS 150 - Fall 2005 - Lecture #4: Verilog - 1 Quick History of HDLs ISP (circa 1977) -
More informationregister:a group of binary cells suitable for holding binary information flip-flops + gates
9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the
More information: : (91-44) (Office) (91-44) (Residence)
Course: VLSI Circuits (Video Course) Faculty Coordinator(s) : Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Chennai 600036 Email Telephone : srinis@iitm.ac.in,
More informationRTL Coding General Concepts
RTL Coding General Concepts Typical Digital System 2 Components of a Digital System Printed circuit board (PCB) Embedded d software microprocessor microcontroller digital signal processor (DSP) ASIC Programmable
More informationVerilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3
Verilog Hardware Description Languages Verilog -- structural: modules, instances -- dataflow: continuous assignment -- sequential behavior: always blocks -- pitfalls -- other useful features Reminder:
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationLSN 1 Digital Design Flow for PLDs
LSN 1 Digital Design Flow for PLDs ECT357 Microprocessors I Department of Engineering Technology LSN 1 Programmable Logic Devices Functionless devices in base form Require programming to operate The logic
More informationProgrammable Logic Devices Verilog VII CMPE 415
Synthesis of Combinational Logic In theory, synthesis tools automatically create an optimal gate-level realization of a design from a high level HDL description. In reality, the results depend on the skill
More informationChapter 10: Design Options of Digital Systems
Chapter 10: Design Options of Digital Systems Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog
More informationField Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
More informationUsing XILINX WebPACK Software to Create CPLD Designs
Introduction to WebPACK Using XILINX WebPACK Software to Create CPLD Designs RELEASE DATE: 10/24/1999 All XS-prefix product designations are trademarks of XESS Corp. All XC-prefix product designations
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but
More informationΔΙΑΛΕΞΗ 2: FPGA Architectures
ΗΜΥ 664 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο 2010 ΔΙΑΛΕΞΗ 2: FPGA Architectures ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Λέκτορας ΗΜΜΥ (ttheocharides@ucy.ac.cy) Some slides adopted from Digital Integrated Circuits,
More informationTLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4
TLL5000 Electronic System Design Base Module Getting Started Guide, Ver 3.4 COPYRIGHT NOTICE The Learning Labs, Inc. ( TLL ) All rights reserved, 2008 Reproduction in any form without permission is prohibited.
More informationSetup/Hold. Set Up time (t su ):
Lecture 10 Agenda Set Up time (t su ): Setup/Hold Minimum amount of time the data is to be held steady prior to the clock event Hold time (t h ): Minimum amount of time the data is to be held steady after
More informationXST User Guide
XST User Guide R 2005 Xilin, Inc. All Rights Reserved. XILINX, the Xilin logo, and other designated brands included herein are trademarks of Xilin, Inc. All other trademarks are the property of their respective
More informationIntroduction. Why Use HDL? Simulation output. Explanation
Introduction Verilog HDL is a Hardware Description Language (HDL) HDL is a language used to describe a digital system, for example, a computer or a component of a computer. Most popular HDLs are VHDL and
More informationSynthesis of Combinational and Sequential Circuits with Verilog
Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two
More informationEECS Components and Design Techniques for Digital Systems. Lec 20 RTL Design Optimization 11/6/2007
EECS 5 - Components and Design Techniques for Digital Systems Lec 2 RTL Design Optimization /6/27 Shauki Elassaad Electrical Engineering and Computer Sciences University of California, Berkeley Slides
More informationChapter 2 Basic Logic Circuits and VHDL Description
Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them. ----- Albert Einstein Like a C or C++ programmer don t apply the logic.
More information