Copyright 1982, by the author(s). All rights reserved.

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1 Copyright 1982, by the author(s). All rights reserved. Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated without fee provided that copies are ot made or distributed for profit or commercial advatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, to republish, to post o servers or to redistribute to lists, requires prior specific permissio.

2 USING A RELATIONAL DATABASE MANAGEMENT SYSTEM FOR COMPUTER AIDED DESIGN DATA by Atoi Guttma ad Michael Stoebraker Memoradum No. UCB/ERL M82/37 25 March 1982 ELECTRONICS RESEARCH LABORATORY

3 This work was supported by the Natioal Sciece Foudatio uder grat ECS ad by the Air Force Office of Scietific Research uder grat

4 USING A RELATIONAL DATABASE MANAGEMENT SYSTEM FOR COMPUTER AIDED DESIGN DATA Atoi Guttma Michael Stoebraker Uiversity of Califoria Berkeley 1. Itroductio There has bee cosiderable iterest i usig relatioal database systems to maage data for computer aided desig (CAD) systems. However, cocers have bee expressed that database systems geerally have bee desiged for other uses ad might ot be well suited to CAD. I additio, there is cocer that relatioal DBMS's are too slow. The purpose of this paper is to report our experiece with implemetig a CAD applicatio i a relatioal DBMS ad comparig its performace with a o-database CAD package. I Sectio 2 we discuss the database schema that was used ad describe the structure of the special purpose CAD package. The i Sectio 3 we idicate the experimets performed ad give the results. Sectio 4 cotais a discussio of the results. Lastly, Sectio 5 idicates areas where a relatioal DBMS was foud to be iadequate as a support tool for CAD applicatios. 2. The Database Schema. The applicatio package bechraarked was KIC, a graphics editor for itegrated circuit desigs developed at Berkeley [2]. A KIC database cosists of a collectio of circuit "cells". Each cell ca cotai mask geometry ad subcell refereces. A complete circuit desig expads ito a tree, with a sigle cell at the root ad other cells, used as subcells, for the o-root odes. Mask geometry ca be associated with each ode i the tree. Durig editig KIC stores a circuit i virtual memory o a VAX 11/780 computer. relatios: Our INGRES schema reflects the above structure ad has five mai cell master (ame, author, master id, defied) cell ref (paret, child, cell ref id, t11-t52) box (ower, use, x1, x2, y1, y2) wire (ower, use, wire id, width, x1, y1, x2, y2)

5 polygo (ower, use, polygo id, vertum, x, y) I the cell master relatio, ame is the textual ame give to the cell ad author is the ame of the perso who desiged it. Master id is a uique idetificatio umber assiged to each cell. It is used for uambiguous refereces to the cell withi the database. The cell ref relatio describes subcell refereces. For example, if the cell "cpu" cotais "register" as a part, the the cell ref relatio cotais a tuple i which paret is the idetifier of "cpu" ad child is the idetifier of "register". T11 through t32 are a 3 X 2 matrix specifyig the locatio, orietatio ad scale of the subcell with respect to the paret. This represetatio of a spatial trasform is the oe geerally used i computer graphics [3]. The box relatio describes mask rectagles. Ower is the idetifier of the cell of which the box is a part. Use specifies the mask layer; e.g. metal or diffusio. X1_ ad x2 are the x-coordiates of the left ad right sides of the box while l_ ad y2 are the y- coordiates of the top ad bottom. A "wire" is a coected path of lies. Each tuple i the wire relatio describes oe lie segmet, givig the coordiates of its ceterlie (x1_, y^, x2, y2) ad its width. Wire id is a uique idetifier for a particular wire. Ower ad use mea the same as for the box relatio. A "polygo" is a solid shape with ay umber of vertices. Oe vertex is stored i each tuple of the polygo relatio. X ad are the coordiates of the vertex, ad vertum orders the vertices (tuples) withi oe polygo. 3.. The Experimet For our test data we used circuit cells from two desig projects at Berkeley. GORDA is a prototype layout for a switched capacitor filter [5], ad deco-1 is a part of the RISC VLSI computer [6,7]. The desig descriptios were traslated from KIC files ad loaded ito the INGRES database. We programmed three represetative CAD retrieval operatios ad measured the speed of our test programs compared to KIC performig the same operatios. The test programs were writte i C ad made calls to the INGRES DBMS [4]. Top-level geometry retrieval. The first program retrieved the geometry data associated with a give circuit cell, ot icludig geometry belogig to subcells. This is the first step i most CAD editig sessios. Geometry retrieval with tree expasio. The secod program retrieved geometry for all cells refereced i a fully expaded desig tree. Geometry for lower level cells was trasformed to its proper positio relative to the root cell. This operatio produces a plot of a etire desig. Retrieval by locatio. The third program retrieved top-level geometry that fell withi a small area i the middle of a cell. This

6 operatio would be used to "widow" a circuit. The tables below show the results of the tests. Geometry Tuples refers to the umber of tuples represetig geometry retrieved from the INGRES database durig each operatio. CPU Time ad Elapsed Time were reported by the operatig system. The msec/tuple figures are time divided by the umber of INGRES tuples. The Relative Time rows give the slowdow factor of our test programs relative to KIC. Circuit GORDA il i Geometry Tuples 592 KIC INGRES CPU Secods i CPU msec/tuple 1 Relative CPU Time i Elapsed Secods Elapsed msec/tuple Relative Elapsed Time Test 1: i j il ] Ii Top Level Retrieval Circuit Geometry Tuples -ti ll it- 41 KIC GORDA 12r779 INGRES "1 i i t CPU Secods CPU msec/tuple Relative CPU Time Elapsed Secods -Ti ll II II -ti ll Elapsed msec/tuple Relative Elapsed Time Test 2: Retrieval with Tree Expasio

7 4_. i i Circuit j! dec0-1 i Geometry Tuples j.448 i KIC INGRES j Geometries i Widow 87 i 85 j i CPU Secods } 75 j 14.5! i CPU msec/tuple j I j Relative CPU Time j 1 i 20 j ] Elapsed Secods } i Elapsed msec/tuple j j i j Relative Elapsed Time 1 j 45 Discussio of Results Test 3: Retrieval by Locatio I Tests 1 ad 2, the factor of three icrease i CPU time for INGRES ca be attributed primarily to the fact that INGRES is a geeral-purpose DBMS while KIC icludes oly fuctios that it requires. Ay DBMS used i place of special purpose code will show some decrease i performace. This cost must be balaced agaist the advatages of usig a DBMS, e.g. simplificatio of applicatio software, data idepedece, etc. The elapsed time measuremets show a larger performace differece, about a factor of five. This is maily because INGRES geometry data is disk residet. KIC geometry data resides i virtual memory, ad sice the tests were ru o a dedicated machie with ample mai memory, KIC's data was actually i real memory. KIC has a spatial bi structure that allows it to quickly isolate geometry i the widow for Test 3. INGRES has o such access method ad must perform a sequetial search. The ew features suggested i the ext sectio may arrow the performace gap. I additio, chagig INGRES to maage a virtual memory database would dramatically improve performace. i 5_. New Features Durig our experimetatio we idetified four features that should be added to a relatioal DBMS to facilitate CAD applicatios. We discuss them i tur. 5/J_. Ragged relatios It would have bee coveiet for a field i a relatio to repeat a variable umber of times. I our database, for example, this would have allowed us to store data for a varyig umber of "boxes" i the cell master relatio, istead of i a separate, box relatio. The

8 cell master relatio could have bee defied by cell master (master id, ame, author, defied, &(use, x1, x2, y1, y2)). where the otatio "&(...)" meas that the group of five fields describig a box is repeated, oce for each box. The wire, polygo ad cell referece relatios could be coalesced with the cell master relatio i a similar way. This revised schema might be more atural for a user to uderstad. I additio, it would speed access to the geometry for a particular cell, sice the geometry would be i oe tuple rather tha distributed across three relatios. We propose this extesio uder the ame "ragged relatios". Oe way to support ragged relatios would be to first provide ordered relatios, which has bee suggested by Stoebraker ad others [8,1l], ad the allow relatios to est, so that a field of a relatio could be a ordered relatio. We are ivestigatig this idea. A database with ragged relatios or ested relatios is ot i first ormal form, ad reflects the hierarchical ature of the data. A laguage that provides just the stadard relatioal data maipulatio operatios must be augmeted before it ca be used with ragged relatios or ested relatios. We are ivestigatig such a augmetatio. 5..2_» Trasitive Closure Our secod test program was required to expad subcells which could est a variable umber of times. This is a operatio similar to a trasitive closure ad does ot correspod to a sigle INGRES query. We have exteded the sytax of QUEL with a * operator to facilitate such tasks. For example: rage of r is cell ref rage of t^ ^s. tree retrieve * ito tree (cell = r.child) where r.paret = ROOT or r.paret = t.cell Here the tuple variable _t rages over the tree relatio, which is the result of the query. The retrieve adds tuples to tree, ad is repeated (with jt ragig over the ew tuples) util there are o ew additios. Some database operatios ivolvig trasitive closure are possible i Query-By-Example [12] ad i the ORACLE system [13]. 5/JL* Access by spatial locatio May CAD programs, like our third test program, eed to retrieve desig data accordig to its spatial locatio. This test would have ru much faster i INGRES if data could be classified accordig to a system of spatial "bis", i.e. by approximate locatio. We are cosiderig addig a spatial bi mechaism to INGRES as a extesio of the secodary idex facility. A two-dimesioal array of bis is defied by a grid. A bi idex is a file cotaiig, for each

9 bi, poiters to all the objects that might overlap that bi. Geometries i a particular area ca be foud quickly by lookig i the idex uder the appropriate bis. For example, a bi idex could be defied by: idex o box is boxbis (mitxl,x2) through max(x1_,x2) by 10, mi(y1,y2) through max(y1,y2) by W). This bi idex is based o a grid of 10 X 10 squares. The mi-max expressios specify the size of each box ad defie the set of bis it could overlap. 5_.4_. Uique idetifiers Codd ad others [9,10] have suggested the usefuless of uique idetifiers for database objects. They should be geerated automatically by the database system ad hadled iterally as a special type. I our applicatio we were forced to maage our ow uique idetifiers for cells, wires, etc. S_. Coclusios INGRES performs typical computer aided desig retrieval operatios cosiderably slower tha special purpose programs. We have suggested a umber of ehacemets that could be made to a relatioal database system that would improve performace ad make the system easier to use for CAD applicatios. We are cotiuig to look for additioal mechaisms alog the same lies. 2* Ackowledgemets This work was sposored by NSF grat ECS Wog-2/82 ad by AFOSR grat Stoebraker/Wog-6/82. 8^. Refereces [l] Held, G.D., M.R. Stoebraker ad E.Wog "INGRES: A Relatioal Data Base System," Proc. AFIPS 1975 NCC, Vol. 44, AFIPS Press, Motvale, N.J. [2] Keller, K. Kic, A Graphics Editor for Itegrated Circuits, Masters Thesis, Dept. of Electrical Egieerig ad Computer Sciece, Uiversity of Califoria, Berkeley, CA. Jue [3] Newma, W.M. ad R.F. Sproull "Priciples of Iteractive Computer Graphics," McGraw-Hill, N.Y [4] Woodfill, J. et al. "INGRES Versio 6.2 Referece Maual," Memo No. UCB/ERL M79/43, Electroics Research Laboratory, Uiversity of Califoria, Berkeley, CA. July [5] The circuit cell GORDA is a layout prototype of a switched capacitor filter made by Jesus Guiea at Electroics Research Labs, Uiversity of Califoria, Berkeley, CA. [6] Patterso, D.A. ad C.H. Sequi "RISC I: A Reduced Istructio Set VLSI Computer," Proc. Eighth Iteratioal Symposium o Computer

10 Architecture, May 1981, pp [7] Fitzpatrick, D.T. et al. "A RISCy Approach to VLSI," VLSI Desig, Fourth Quarter (October 1981), pp (Also appears i Computer Architecture News, March 1982.) [8] Stoebraker, M. ad J. Kalash "TIMBER: A Sophisticated Relatio Brouser," Memo No. UCB/ERL M81/94, Electroics Research Laboratory, Uiversity of Califoria, Berkeley, CA. December [9] Codd, E.F. "Extedig the Database Relatioal Model to Capture More Meaig," ACM Trasactios o Database Systems, Vol. 4, No. 4, December 1979, pp [10] Lorie, R.A. "Issues i Database for Desig Applicatios," IBM Research Report RJ3176 (38928) 7/10/81. [il] Lorie, R.A., R. Casajuaa, ad J.L. Becerril "GSYSR: A Relatioal Database Iterface for Graphics," IBM Research Report RJ2511 (32941) 4/24/79. [12] Zloof, M. "Query-By-Example: Operatios o the Trasitive Closure," IBM Research Report RC 5526 (Revised) (#24020) 10/29/76 [13] "ORACLE SQL Laguage - Referece Guide," Copyright by Relatioal Software Icorporated, October 1980.