ECE 2300 Digital Logic & Computer Organization. Single Cycle Microprocessor

Size: px

Start display at page:

Download "ECE 2300 Digital Logic & Computer Organization. Single Cycle Microprocessor"

Scott Knight
5 years ago
Views:

1 ECE 23 Digital Logic & Computer Organization Spring 28 Single Cycle Microprocessor Lecture 5:

2 Announcements HW 6 released (with a practice question) Lab 5 prelab (A) due tomorrow Lecture 5: 2

3 SRAM vs. AM SRAM advantages and disadvantages Usually on the same chip with microprocessor Fast access (+) High power ( ) Relatively high area & cost per bit ( ) AM: main memory is stored in AM cells Typically off-chip Single transistor storage cell (+) Higher density lower cost/bit Lower power/bit Slow ( ) Need periodic refresh to retain data Lecture 5: 3

4 Boolean algebra Course Roadmap (Part ) Combinational logic and minimization Logic functions CMOS gates Binary arithmetic and s Latches and flip-flops Counters Verilog Finite state machines Hazards, timing, clocking Memories Lecture 5: 4

Organization of a Computer Part 2: Computer Organization ä ä 4HEä ORGANIZATIONä OFä Aä COMPUTER ä SHOWINGä THEä läveä CLASSICä COMPONENTS ä4heä Lecture 5: 5 Rä GETSä INSTRUCTIONSä ANDä

5 Organization of a Computer Part 2: Computer Organization ä ä 4HEä ORGANIZATIONä OFä Aä COMPUTER ä SHOWINGä THEä läveä CLASSICä COMPONENTS ä4heä Lecture 5: 5 Rä GETSä INSTRUCTIONSä ANDä DATAä FROMä MEMORY ä )NPUTä WRITESä DATAä TOä MEMORY ä ANDä OUTPUTä READSä DATAä Lecture 5:!8 MORY ä#ontroläsendsätheäsignalsäthatädetermineätheäoperationsäofätheädatapath ämemory äinput äandä

6 Let s Build a Microprocessor! PC Inst. RAM IMM MB FS MD MW BS Decoder SE(OFF,) SE IMM +2 Adder MB MP F m F V C Z N M_address Data_in Z Z N N C V Data RAM MW MP BS MD Lecture 5: 6

7 The Basic Processing Cycle Operation Data Out Read data from two registers Perform an operation Place the result into a register All three steps performed in clock cycle Lecture 5: 7

8 Register File () Collection of 2 k n-bit registers Control inputs Source address A Source address B Destination address Load destination register with Data inputs Input data Data outputs Output data A Output data B k k k n Clk n n Lecture 5: 8

9 Example Organization Decoder I I EN Y Y Y2 Y3 n Reg EN D Reg EN D Reg 2 EN D Reg 3 EN D MUX 2 3 MUX 2 3 n n Example with 4 registers. Typically have 32 or more. Lecture 5: 9

10 Instruction Execution add Data Out ADD R, R, R2 operation destination register source registers Lecture 5:

11 Instruction Execution Operation Data Out ADD R, R, R2 CLOCK Operation add [R] [R2] Data Out [R]+[R2] Lecture 5:

12 Instruction Execution Operation Data Out ADD R, R, R2 SUB R3, R2, R CLOCK Operation add sub [R] [R2] [R2] [R] Data Out [R]+[R2] [R2] [R] Lecture 5: 2

13 Operations With Constants Operation SE IMM MB Data Out ADDI R3, R3, Constants are called immediate values Sign extend (SE) IMM to the width of to perform correct two s complement operation Why? May not have enough bits in instruction (later) Assume IMM is 4 bits and is 8 bits wide Lecture 5: 3

14 Reading and Writing Memory SE IMM MB Operation M_address Data_in RAM MW MD Most data are held in memory (RAM) Must be moved into a register in order to operate on it Data will also move out of registers into memory To make room for other data To move it to permanent storage (e.g., disk) Lecture 5: 4

15 Reading Memory ( Load ) xx SE IMM = 4 MB= add M_address Data_in RAM MW= MD = Example: LOAD R3, 4(R) // R3 <= M[R + 4] Step : Form the memory address by adding the value in R (base) with the immediate 4 (offset) Step 2: Read the data at that address in RAM and place it in R3 Lecture 5: 5

16 Writing Memory ( Store ) xx SE IMM = MB= add M_address Data_in RAM MW= MD =x Example: STORE R2, (R) // M[R] <= R2 Step : Form the memory address by adding the value in R with the immediate Step 2: Write the value in R2 into the RAM at that address Lecture 5: 6

17 Control Unit Regulates the interaction between data and operations on data (i.e., datapath) Series of control words control the datapath to perform a sequence of operations The sequence of operations performed by the CU may be affected by the Condition Codes Z: Zero N: Negative Also V: Overflow and C: Carry out Lecture 5: 7

18 Datapath + Control Unit IMM MB V FS C MD N Z MW CU SE IMM MB F m F V C Z N M_address Data_in RAM MW MD Control Word IMM MB FS MD MW k-bit register addresses immediate value function select memory write load register register/immediate select /memory select Lecture 5: 8

19 Sequence of Operations IMM MB V FS C MD N Z MW CU SE IMM MB F m F V C Z N M_address Data_in RAM MW MD IMM MB FS MD MW R2 <= R + R R <= M[R2] M[R2] <= R x ADD xx ADD xx ADD x Lecture 5: 9

20 Sequential (Shift and Add) Multiplication Unsigned multiplication: A 2 A A by B 2 B B A 2 A A B 2 B B (A 2 A A )ÎB R <= M[] // load A from M[] R2 <= M[] // load B from M[] R3 <= // initialize R3 (P) = (A 2 A A ) ÎB (A 2 A A ) ÎB 2 P 4 P 3 P 2 P P P = AxB Assumptions: () A, B are initially in memory; (2) P will also be put back to memory (*) R4 <= R2 & // R4 = lsb(b) R2 <= SRL(R2) // shift B right if (R4) R3 <= R3+R // if lsb(b)=, P=P+A R <= SLL(R) // shift A left if (R2) goto (*) // repeat until B= M[2] <= R3 // store P to M[2] Pseudo code Lecture 5: 2

21 Next Time More Single-Cycle Microprocessor Lecture 5: 2

ECE 2300 Digital Logic & Computer Organization. More Single Cycle Microprocessor

ECE 2300 Digital Logic & Computer Organization. More Single Cycle Microprocessor ECE 23 Digital Logic & Computer Organization Spring 28 More Single Cycle Microprocessor Lecture 6: HW6 due tomorrow Announcements Prelim 2: Tues April 7, 7:3pm, Phillips Hall Coverage: Lectures 8~6 Inform