The following is a procedure for extracting a layout, doing a layout vs. schematic check, and then simulating the extracted layout with Cadence.
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- Gyles Summers
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1 The following is a procedure for extracting a layout, doing a layout vs. schematic check, and then simulating the extracted layout with Cadence. (This might not be the best way, but it works!) 1) Realize a schematic cell view fully with real transistors in virtuoso. Run continual DRC's during this process to ensure that you aren't making a million mistakes. 2) When satisfied, click on verify ---> extract... 3) When the extractor window pops up, choose: extract method, flat join nets with same name set switches, extract_parasitic_caps, keep_labels_in_extracted_view leave all others as the default click ok 4) Go to the library manager and open the extracted view of the layout 5) Click on verify ---> lvs... 6) An lvs form contents window will open along with the lvs window 7) Close and ignore the lvs form contents window 8) Click on the lvs window
2 9) Leave all defaults alone 10) Be sure that the paths point to the correct library/cell/view 11) Click run and wait for a window to pop up and say that your job succeeded 12) Click on output and study the si.out file. If it says the net lists match you can go ahead. If they don't, use the information in this file to either fix your layout or tweak the schematic. You must go back to step 1 and repeat until the happy message is displayed. 13) Close the si.out file and the lvs window 14) Make a directory in your simulation area under the cell you are working on called cell_name_extsim. This is what the path should look like: /n/15/yourname/cadence/simulation/input_stage_extsim 15) In the virtuoso extracted cell view, click on tools -->simulation-->spectre 16) A spectre option will appear in the bar of choices at the top of the window between route and ncsu 17) Click this new spectre-----> initialize... 18) The initialize environment window will open. Clear the simulation run directory box and copy and paste the path from 14 there. Click ok. 19) A window will pop up telling you that the directory exists but has not been used in SE. Click ok to initialize the simulation environment. 1
3 20) Click on spectre---->stimulus-----> edit stimulus file 21) An editor will open the file spectre.inp. Since your cell view is only made of transistors/resistors/caps you need to connect voltage sources etc. to get it working. This file is where to declare these items. You will need to make adjustments to this file so that it will work with your specific circuit and you can find details on this in the online documentation for spectre: /opt/ic****/doc/spectreref/spectreref.pdf Below is an example of what would be used for a simple inverter circuit:!!!be sure that your pins in the inverter layout are called exactly (gnd!, vcc!, vin, vout) // Spectre Source Statements v0 (vcc! 0) vsource dc=5 type=dc v2 (vin 0) vsource type=pulse val0=0 val1=5 period=20n delay=1n rise=.1n fall=.1n width=10n 22) Compose your spectre.inp in the editor, save and close it. 23) Click on spectre---->stimulus-----> edit analysis/options file 24) An editor will open the file spectre.sim. This is the file where you specify your analysis to run. // specifies a comment in spectre so uncomment the dc1 and tran1, make the stop time something sensible (100nS), then save and close the file. It should look something like this: // Spectre Analyses and Output Options Statements // Output Options simoptions options 2
4 //+ reltol = E-03 //+ vabstol = E-06 //+ iabstol = E-12 //+ temp = 27 //+ save = allpub //+ currents = selected // Analyses dc1 dc oppoint=logfile homotopy=all tran1 tran stop=100n errpreset=moderate 25) Click on spectre---->stimulus-----> model include files 26) The model include files window pops up. Click on add file and a place to put the path pops up. Enter the correct path for your process and continue. I don't think that the syntax option matters so leave it spice 27) Click on spectre---->netlist and simulate 28) The netlist and simulate window pops up. Click Browse and select the extracted view you are working on in the library browser. Once it is highlighted, close the library browser. Be sure that the Run Actions: netlist, create run file, and simulate are selected. Leave all else alone and then click ok. Wait until a window pops up. It will either tell you that there was a success or that there was a failure. 29) To fix a failure look at the following files and try to figure out what happened to you. It is quite common to have a syntax error in the spectre.inp, spectre.sim, or typographical error the model include path. Good luck! spectre--->show outputs---->show run log-->show background run log spectre--->show outputs---->show output spectre--->show outputs---->show global error 30) If your analysis job succeeds, you can then do: 3
5 spectre--->waveform tool This will open three windows, a waveform window, calculator window, and a results browser window. Go to the results browser window and click on si.raw/. A tree of Run1, dc1-dc, and tran1-tran will appear. Click on the tran1-tran and another branch of possible selections will appear. If you are doing the inverter example, vin and vout will appear. Click on vin. The field in the calculator window should now be filled. Click on the plot button in the calculator window and your waveform should be plotted in the waveform window. Go back to the results browser and click on vout. The field in the calculator will update. Click plot in the calculator window and vout will be plotted along with vin in the waveform window. Enjoy! 10/08/04 DSS 4
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The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules.
Page 1 of 5 CADENCE TUTORIAL Creating Layout of an inverter: click on File->library->new a Create Library form appears, fill it as follows: in the name field enter: inverter select "Attach to existing