EE 330 Spring Laboratory 2: Basic Boolean Circuits

Transcription

1 EE 330 Spring 2013 Laboratory 2: Basic Boolean Circuits Objective: The objective of this experiment is to investigate methods for evaluating the performance of Boolean circuits. Emphasis will be placed on the basic CMOS inverter but the concepts are applicable to larger circuits. Time domain behavior of the inverter will be considered. Some of the file creation and manipulation commands that will be required in this experiment were covered in the previous laboratory experiment. In this experiment, blue font will be used to provide details on how to implement specific tasks. Most of the comments in blue font are a review of what was done in the previous experiment so can be skipped if you already know how to complete the required tasks. Boldface will be used to denote major commands and text entry items will be the material between < and >. Part 1.1: Introduction A digital inverter with Boolean input A and Boolean output Y is shown in Fig. 1a Page 1 of 10 Update Date: 1/25/2013

2 Figure 1 Digital Inverter a) Gate Representation b) Simple Transistor Implementation c) Transistor Implementation Showing Bulk Connections This gate level representation provides no detail about the underlying circuit used to realize the gate. Fig. 1b shows transistor level detail for the basic CMOS implementation but does not show how the bulk is connected in the circuit. The representation in Fig. 1c shows all connectivity of the CMOS inverter. In the latter view, the input and output variables are labeled as voltage variables rather than as Boolean variables. Part 2 Simulation of a CMOS Inverter In this section we will focus on the creation of a schematic of a CMOS inverter and on the simulation of this inverter in Spectre. We will create this schematic in a new library named Lab2 that will be added to your libraries in the Library Manager window. Part 2.1 Attaching technology information In the previous laboratory experiment, a simple circuit consisting only of resistors and capacitors was simulated. In this experiment an inverter implemented with transistors will be simulated. Initially, create a new cell named 'inverter' in schematic view. To use the correct models for the transistors, the Technology in which the inverter is designed must be associated with the schematic. By associating a technology (sometimes termed a technology file ) with a design, both the semiconductor manufacturer and the technology that manufacturer will use to fabricate the circuit is specified should we choose to fabricate the design as an IC. For the purposes of this course, we will use the 0.5μm CMOS process technology from ON Semiconductor. ON Semiconductor was a spin-off from Motorola and purchased a company called AMI who provided this 0.5um process to universities for many years prior to the acquisition of AMI by ON. In the context of this process technology, an occasional reference to AMI may still be made even though the company no longer exists. When the process association is complete, the ON 0.5μm process information will automatically be used in our designs. Process information in a technology file includes critical parameters such as the minimum device size, the available layer masks, the supply voltage level, and a detailed model of the transistors. Create a new library named Lab2 (or any other name you choose) in the Library Manager Window. The Library Manager Window (LMW) can be opened by clicking on the Tools button in menu bar that appears in the Command Interpreter Window (CIW) in the Konsole. The new library that you will name Lab2 can be added by clicking on the File button in the LMW, then clicking on New in the drop down menu and then clicking on Library in the drop right menu and then typing <Lab2> in the Name box and then click on the OK button. There will be a Technology File for New Library window that will appear. Simply close this window. Attach the AMI 0.6u C5N technology file to the Lab2 Library. This can be accomplished two ways. One way is to add it when the Technology File for New Library window appeared when you created the Lab2 library. But since we closed that window, we will present the other way here. In the CIW select Tools in the menu Page 2 of 10 Update Date: 1/25/2013

3 bar. A Technology Tool Box window will appear. Click on the Attach button. An Attach Technology Library to Design Library window will appear. Select the library Lab2 by scrolling down in the Design Library selector. Then select NCSU_TechLib_ami06 by scrolling down in the Technology Library selector. Click OK. Check to be sure it has been attached. Do this by highlighting Lab2 in the LMW, clicking on Edit in the menu bar of the LMW, and clicking on the Properties button in the drop down menu. The.ami06 technology should appear in the techlibname field. Part 2.2 Creation of a Schematic Consider an implementation of the CMOS inverter of Fig. 1c in the ON 0.5μ CMOS process. Use a 5V power supply and size the devices M 1 and M 2 with the drawn dimensions given in Table 1. Table 1: Device Sizes for Inverter W L M 1 1.5u 0.6u M 2 4.5u 0.6u Create a schematic view of the inverter in a new cell in your Lab2 library (for convenience use the name Inverter for this cell). For the NMOS and PMOS transistors, use the cells nmos4 and pmos4 from the NCSU_Analog_Parts library, respectively. NOTE: The transistors should have 4 terminals, NOT 3. When editing the transistor properties, the lengths and widths need to be in the fields labeled Width and Length, not in the Width (grid units) or Length (grid units) fields. When entering numbers in the Cadence design and simulation environment, you can use engineering notation such as k (10 3 ), M (10 6 ), m (10-3 ), u (10-6 ), n (10-9 ), etc. The suffix should be written right next to the number without spaces. For example, 10*10-9 can be entered as 10n or 10e-9 but not as 10 n. The labeled voltages on the schematic of Fig.1c include the voltage VSS which is often set at ground but for generality we have designated it as VSS. These labeled voltages must be designated with pins on the schematic you enter in Cadence. Pins can be of different types depending upon the intended use of the pin. To add pins, go to Add --> pin. The process of adding a pin is the same as adding labels, that is, separate multiple pins by a space and then place them on the schematic. Be sure to wire the pins to the appropriate wires! The voltages VDD and VSS should be bidirectional (inputoutput) pins. The voltage designated as VIN should be in input pin and the voltage designated as VOUT should be designated as an output pin. Also note that the specific pin will be automatically connected to the wire labeled with the same name. Be careful while naming wires and pins. Later labs will require you to reference these, and all references are case sensitive. Pick a labeling style and stick to it! Page 3 of 10 Update Date: 1/25/2013

4 Part 2.3 Symbol Creation To re-use the inverter we just created efficiently, we need to create a symbol for our schematic design. Go to Design Create Cellview From Cellview. If you think the information automatically filled is correct, press OK. A window with the symbol will be opened. Use the buttons on the left to Change the symbol view to make it look like an inverter. Make sure you keep the pins consistent. This process simply creates a graphic - no wiring or electrical connections are used in the lines. The critical electrical parts are the red squares where the exterior circuit will attach to the graphic. Part 2.4: Inverter transient response simulation Now that we have a symbol for our inverter, let us set up the test bench. Create another schematic called test_inverter to test the design. The test bench is shown below. Figure 2: Inverter simulation test bench Use the voltage sources from analoglib. For the pulse input source, you can use either the vpulse or the vsource component from the analoglib library. You will need to apply an input square wave of frequency 1MHz with magnitude of 5V and rise and fall times of 1 pico seconds each. To instantiate your own inverter, use the instantiation procedure as you would for any other component from analoglib but choose the inverter cell instead from your own lablib library. Set the dc power supply voltage to 5V and the load capacitor to 1pF. Check and Save your work and correct all errors or warnings. Open the Analog Design Environment and check the Setup parameters first. Click on Setup Simulator Directory Host and check the Project Directory. This is the directory where simulation results are stored. It is recommended that you always store your simulation data on the local hard drive. To ensure this, set your project directory to /local/[username]/cadence/simulation. If you see /home/username then you should be aware that some simulations might run unusually slow and could take your entire ENGR disk quota. Page 4 of 10 Update Date: 1/25/2013

5 You can make this choice the default for all of your future Cadence sessions by creating a new file called.cdsenv in your home directory and adding the following line to it (with your username). asimenv.startup projectdir string "/local/[username]/cadence/simulation " Set up the transient analysis to run long enough for 5 complete input cycles. Select the input and output voltages for plotting and start the simulation. Did you create labels for those nodes of interest (recall how we used the labels vin, vmid, and vout in lab1)? Debugging and evaluation of results become easier with labels. Show this analysis to your TA. Part 2.5: Inverter transfer characteristics simulation Modify the source and simulation environment to obtain the dc transfer characteristics (VOUT vs VIN) of the inverter for inputs voltages between 0V and 5V. At what value if VIN are the input and output equal? What is the maximum value of VIN that can be applied and still keep the output near 0V? What is the minimum value of VIN that can be applied and still keep the output near VDD? Show the transfer characteristics to your TA. Part 2.6: Inverter driving a load Increase the load to 10 pf. What do you notice at the output? What if you have a 100 pf load? Or a 1uF load? Explain what you think happens. Increase the width of the transistors of the inverter by a factor of ten (i.e. Wp=45u, and Wn=15u). Revert back to a 10pF load and simulate. What happened, and why did it occur? Show your plots to your TA. Part 3: Cascaded Inverters We will now cascade two inverters and analyze how the signal propagates from one stage to the other. Modify your inverter_test cell so it looks like the following figure: Page 5 of 10 Update Date: 1/25/2013

6 Figure 3: Cascaded inverter simulation The antenna on top of the vdc source and the power supply pin of the inverters is a visual aid and a method of connecting multiple power supply nets together. The antenna shaped cell is called vdd and is available from analoglib. Run a simulation and plot the three voltages of the circuit: input of inverter 1, output of inverter 1, and output of inverter 2. Label these nodes before running the simulation. Show this simulation to your TA. Compare the output of inverter 2 with the input of inverter 1. Do they look the same? Do you see any loss of signal integrity? Is there any noticeable delay? Part 4: Inverter Simulation with Verilog HDL inside ModelSim Throughout this course, we will be using Verilog to simulate and design digital circuits and systems. To alleviate some of the stress of learning Verilog for the final labs and project, this lab includes a short tutorial on how to simulate the digital inverter using Verilog HDL in ModelSim software. This is common simulation software for digital designers in industry and has many features that will not be used in this class (ECprE 465 is the class to take if you are interested in digital VLSI). Follow the steps below for running ModelSim, creating an inverter behavioral file in Verilog HDL, creating a testbench, and finally running a simple simulation. 1. First, download ModelSim_env.txt from the Lab page on the lab website ( and place in the Home directory. On a terminal, enter the command below to source the path of the ModelSim software. source ModelSim_env.txt Once the script finishes running, you can now run ModelSim by typing: vsim & 2. Once ModelSim opens, the next step is to create a new project Page 6 of 10 Update Date: 1/25/2013

7 Click on File, then New, then choose Project on the drop down menu Enter your project name (in this case the project is called inverter - different than the image below) Choose your project location (this project is stored at /ee330/lablib/inverter ) The default library name should be work. Click OK. 3. You will be asked if want to create the project directory. Click OK button 4. Next you will be presented with the Add Items to Project Dialog. While you can use this dialog to create new source files or add existing ones, we will not be using this option for this lab. We ll add source files later so just click on the Close button 5. You now have a project by the name of inverter. 6. Now we want to add a new file to our project. Page 7 of 10 Update Date: 1/25/2013

8 Right click in the project area, choose Add to Project, and choose New File Choose Verilog as the file type In the File name: box enter the desired file name, in this case the file is named inverter.v (once again this is different than the image) Click on the OK button The inverter.v file has been added to your project. 7. Double-click on the inverter.v file to show the file contents. You are now ready to specify the inverter module s functionality. Remember from prior coursework that there are 2 main ways of specifying a module in Verilog. One is a functional view where the logic is explicitly defined in terms of AND s, OR s, and other logic that can be converted directly into gates. The other method is called a behavioral view, where the logic is more indirect. A behavioral description often uses conditional statements and loops. 8. We compete the inverter specification as shown below: The line `timescale 1ns/ 1ps is located at the top of the file. The Verilog language uses dimensionless time units, and these time units are mapped to real time units within the simulator. The identifier `timescale is used to map to the real time values using the statement `timescale <time1> / <time2>, where <time1> indicates the time units associated with the #delay values, and the <time2> indicates the minimum step time used by the simulator. Note: Be sure to use the correct (`) character. The (`) is the not the single quotation mark ( ) and is typically located on the same key as the ~. If you have errors in your file, this may be the culprit. The inverter module is also declared using module inverter(); and endmodule, but the ports are left for us to define. Be sure to save the changes to the inverter.v file by clicking on File and choosing Save. `timescale 1ns/1ps module inverter (Vin, Vout); input Vin; output Vout; Page 8 of 10 Update Date: 1/25/2013

9 wire Vout; assign Vout = ~Vin; endmodule 9. We also want to add a testbench and again follow Steps 6 8 to add inverter_tb.v. Then we add the functionality of the testbench module as shown below. `timescale 1ns/1ps module inverter_tb(); reg Vin; wire Vout; inverter inv(.vin(vin),.vout(vout) ); initial begin Vin = 1'b0; end always #20 Vin <= ~Vin; Endmodule Notice that the inputs of the inverter module are now defined differently. The inputs of inverter.v are given values (like applying a bias from a voltage source on a real test bench to a circuit on a breadboard) and the outputs are observed to see if they match expectations. More detailed testbenches can be written and the skill of writing good testbenches is heavily desired. Often the testbench takes longer to write and requires more skill than the actual module, and thus a good testbench will be thorough but efficient to reduce wasted resources. 10. After saving both inverter.v and inverter_tb.v, we want to check the syntax of both files. Click on the Compile Menu and select Compile All If the syntax was correct, a checkmark will appear next to each file If the syntax was incorrect, the window at the bottom will list the individual errors. 11. Now it s time to simulate the design. Click on the Simulate menu and choose Start Simulation Expand the selection for the work library by click on the + symbol on the left. Select inverter_tb Uncheck the Optimize Design box and click OK button 12. Next we create a simulation waveform window. Click on View menu, choose New Window, then choose Wave Add the signals that would like to monitor by dragging the signal from the middle pane to the waveform window 13. We are now ready to simulate the design. Page 9 of 10 Update Date: 1/25/2013

10 Enter 80ns as the length of time we would like to simulate for in the Run Length box and click the Run icon. 14. Our simulation is complete. Take a screen shot of the final waveform to include in your lab report. Does this waveform match your expectation of an inverter? Why or why not? What is wrong with this waveform when comparing to reality? How will this affect simulations of more complex logic? Deliverables: 1. Inverter Transient Plot 2. Inverter Transfer Characteristics 3. Inverter Load Simulation 4. Cascaded Inverter Simulation 5. Inverter ModelSim Waveform 1/25/2013 Page 10 of 10 Update Date: