ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

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1 University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2019 HW5: Delay and Layout Sunday, February 17th Due: Friday, March 1st, 11:59pm Problems: All problems should use the AMI 0.60u C5N (3M,2P,high-res) technology setup in previous homeworks. For extra Cadence help refer to 1.htm and Piazza. This manual is for the older version of Cadence, but most steps are similar to what we are currently using with a different GUI. 1. Using Cadence simulation, what is the equivalent source-drain resistance R ds for a W = L = 1.5µm transistor with V gs = V ds = V dd = 5V (NMOS) or V gs = V ds = V dd = 5V (PMOS)? Answer for both NMOS and PMOS transistors. Include description of test circuit, circuit schematics, and simulation results in homework turnin. Part of the question is designing and understanding your test setup. 2. From a Cadence simulation, what is the RC time-constant for: (a) one transistor (W = L = 1.5µm) charging another transistor s gate input of the same size? (b) a transistor (W = L = 1.5µm) charging the gates of 4 transistors of the same size? (c) a transistor (W = L = 1.5µm) charging the gate of a single transistor 4 times the size of the driving transistor? (d) How do your answers to (a), (b), and (c) relate? Include description of test circuit, circuit schematics, and simulation results in homework turnin. Part of the question is designing and understanding your test setup. 3. According to your first-order transistor model from problem 1, what output does a CMOS inverter produce when V in = V dd, V 2 dd=5 V, V thn =800 mv, and V thp =-800 mv. Assume R on,p = R on,n. 4. Consider our MOS technology with the following parameters: V DD = 5V V T 0p = V T 0n = V T 0 = 0.8V 1

2 µ n = 530cm 2 /(V s) and µ p = 200cm 2 /(V s) t ox = 14.1nm λ = 0 ɛ ox = 3.9ɛ 0. (a) Using Cadence, design a CMOS inverter (i.e. size the transistors) such that the switching voltage, V th = 1/2V DD. Submit both the schematic and VTC verifying your design. (b) Using the Vpulse design a test schematic to measure the propagation delay and rise/fall times of your inverter from part (a) with a rail-to-rail input waveform with a period of 4ns, pulse width of 2ns, and rise/fall times of 10ps. Load your inverter with an identical inverter for your delay measurement. Submit the test schematic, input/output transient waveforms, and your delay measurements (propagation and rise/fall times). Left click Add Instance select vpulse from NCSU Analog Parts library. Fill the rest of the boxes. The figure below shows the input pulse that we have specified is bounded between 0 and 5V. It has an initial delay of 1ns, rise and fall time of 1ps and high/low duration of 2ns. In the Analog Design Environment go to Analyses Choose... Set the transient analysis with Stop Time as 8n. We have specified a transient 2

3 analysis from 0 to 8ns. Left click Outputs To be Plotted Select on Schematic. Select the input and output of the inverter. Refer to the previous section, DC analysis, for the necessary steps. The ADE window should look like the picture shown below. Run the simulation by pressing on the green traffic light icon. After few seconds you should be able to see the results of the transient analyses. Note: Make sure to save your schematic every time before simulation, or you will get an error. (c) Design a test schematic to measure the propagation delay of your inverter using a more realistic input. The input should be created by passing the Vpulse from part (b) through your inverter from part (a). Your inverter should still be loaded with an identical inverter. Submit the test schematic, input/output transient waveforms, and your delay measurements (propagation and rise/fall times). (d) Measure the avg power over 4 periods using the calculator to plot the average current through your inverter. 5. Cadence Symbols and Layout This problem is to complete the flow from schematic to layout and verification of your inverter from problem 4. (a) For the inverter you designed in problem 4, create a corresponding symbol. Submit your drawn symbol and schematic with your homework. The schematic is almost the same as before. But you need to add pins for the schematic. Left click Create Pin. In the Pin Names box type the following pin names: in, out, vdd, gnd. Also change the direction of the pins to input for in, output for out, Input/Output for vdd and gnd. A good example of schematic is show below. You can define the pin names as you wish. 3

4 The symbol editor lets you create a black box description of a cell using labels, pins, shapes, notes, and a selection box. Symbols make your design more readable, as you can use them in more complex designs, instead of individual transistors. In the Library Manager click once on your own library. Then left click File New Cell View. Select schematicsymbol and the View Name box will be automatically filled with symbol. Then the Viutuoso Symbol Editor should show up. Then click Create Shape to build the symbol for your schematic. A good example of symbol is shown below. Then we need to add pins to the symbol. Left click Create 4

5 Pin. In the Pin Names box type the following pin names: in, out, vdd, gnd. Also change the direction of the pins to input for in, output for out, Input/Output for vdd and gnd. Change the type to acthi. You are going to start placing the pins in the symbol in the order specified in the Pin Names box, i.e. first you will place the in pin, then out pin. The pins look a little different from the ones in the schematic, so be careful. You will notice that it is a box with a line attached. The end of the line will have the pin name. The box is the actual pin, so it must point AWAY from the rest of the symbol. Next we want to add label to the symbol. Left click Create Label... The last thing to add is a selection box. This will tell the software how much of the symbol is actually used. Create Selection box automatic. The symbol is now finished. (b) For the inverter you designed in problem 4, create the corresponding layout. Submit your layout with your homework. In Library Manager click File New Cell View, select Type to be layout and view will be filled with layout automatically. 5

6 After you create layout cellview, LSW window should show up as below. 6

7 Since we are using the AMI 0.6u technology, we only have an nwell process to use. Thus, the substrate will be a p-type substrate. We can always assume that the background is a p-subtrate. Now we will create a pmos transistor first. To do that, we need an nwell layer in which the pmos transistor will be formed. Note: You may adjust the minimum distance between the grids. In order to do it, in the Virtuoso Layout Editing window select Options Display. A new window will open. On that window, change Minor Spacing to a value that you want. In order to work efficiently, you can adjust it to 1 lambda which is 0.3 (it is actually 0.3u but in that window it will be written as 0.3). Here are some hotkeys that I have found to be very useful when designing layouts: Move about the layout view screen keyboard arrows (up, down, left, right) Fit entire layout onto screen f Zoom in/out Ctrl/Shift z Cancel previous command Esc Reveal all mask layers within each layout cell Shift f (Use Ctrl f to hide these layers) Properties q Create path p (Convenient for making interconnections between I/O pins of layout cell; need to select mask layer first from LSW window) Create rectangle of mask layer r (Select mask layer first from LSW) Create pin Ctrl p (Select mask layer first from LSW) Instantiate layout cell i Select more than one mask layer simultaneously Hold down Shift and click on each layer (Use Ctrl to deselect a particular layer) Undo u Copy c Delete d Move m Stretch s (Point to edge of mask layer first using mouse cursor) Ruler k (Erase ruler Shift k) Select nwell in LSW window, and move cursor to layout window. Type r, just click on the left mouse button to draw the rectangle of n-well region. If you want to change the dimension after drawing, move your cursor to the side where you want to extend or shorten such that the side is highlighted and then type s (stretch). The side will move with your cursor. Note: The ruler shown below can be invoked by typing k, the numbers represent the length in um (micrometers). You do not have to necessarily follow the dimensions shown below. In fact, it is probably a good idea to play around 7

8 with the lengths and widths in order to see how small a mask layer you can create without violating any of the design rules. Likewise, draw the nselect and pselect layers as shown in the figure below. The pselect is where you are creating the pmos transistor since this is where the p+ diffusion is going to be formed. Draw the p+ active layer on your layout as shown in the figure below. The orange shaded rectangle is the p+ active regions. The green shaded rectangle is the n+ active region. Next, draw the poly layer to form the gate of the transistor. The size of the pmos transistor shown below has W=1.5um and L=0.6um. Next we need to connect the active regions to metal lines so that they can be routed. The figure below shows the metal1 layer (blue line-shaded polygons) is connected to the active region by an active contact (cc, which is solid black). Remember that the design rule usually restricts the size of the contact to be 2lambda * 2lambda, which is 0.6u * 0.6u. The nselect creates an n+ diffusion in the nwell. This is the body pin of the pmos transistor, which should be connected to power (vdd). We ll touch on how to connect to the power supply later. 8

9 Next, you can proceed to create the nmos transistor but this time your nmos needs to be created in the nselect layer while the p+ diffusion of the nmos is in the pselect. The size of the nmos chosen in this design has the same dimension as the pmos (channel length 0.6um, width 1.5um). Note that since we are using an nwell technology, we don t need an explicit well for the nmos transistor (the pwell) since the background is p-substrate. The figure below shows the inverter. 9

10 The region between the two transistors would be used for pin definitions and for routing signals from one layout cell to another. The more the distance between the nmos and the pmos transistor, the more connections can be routed 10

11 and less problems to worry about in the future when designing big cells. However, a large distance may be inefficient and result in a very big layout. But for the sake of learning, we would rather choose to go with a large distance of around 15um. The gate of the transistors needs to be connected to the metal1 lines for it to be accessed. To do that there are some ready-to-use macros available for making contacts. To access a macro cell which has a poly-metal1 combo with a single contact, instantiate the cell M1 POLY (note capital letters) from the library NCSU TechLib ami06. Similarly, to access a metal1-metal2 combo with a via, instantiate the cell M1 M2 from the NCSU TechLib ami06 library. These cells will appear as a black box. To see through the cell, type Shift -f. This will make the cell visible. Remember that you cannot update this cell, since it is a standard library cell. The figure below shows the connection. The red-shaded polygon with a black square at the center and blue borderline is the M1 POLY contact. The blue-shaded polygon with a pink square at the center and pink borderline is the M1 M2 contact. 11

12 For simulation purposes and standard cell design rules, it is necessary to add the pin layer. They are identical in purpose to the input/output and vdd/gnd pins in the schematic view. Power and ground rail pins should be declared as Input/output. It would not be a bad idea to label your pins with the text layer, but make sure to name the labels the same as the pins in your schematic and put them on top of the labeled wires. Click on metal2 in the LSW window. Then press Ctrl-p in the layout editor window. A window 12

13 will pop up. Enter the name in for labeling input. Choose Display pin name option and define the pin as input. Then click on the left mouse button with the cursor placed at the top left corner of the metal2 square to be labeled. Then drag the mouse to the right bottom corner of the same metal2 square to be labeled. Click one more time inside the metal2 square to place the text. Do the same steps for placing an out pin except for the fact that you declare the pin as output. Next, select metal1 in LSW window, and type Ctrl-p. Type vdd for Temrinal Names and select I/O Type as Input/Output. The rest is the same as before. 13

14 (c) Perform a DRC and LVS on your inverter layout to ensure it passes the design rules and matches your scehmatic. Submit proof of passing both the DRC and LVS with your homework. Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC on the layout. The DRC is a step taken to prompt us of any violations. To run the DRC, choose DRC... from the Verify menu in the layout view window. A pop-up menu will appear as below. Click ok to run DRC. Cadence then runs the DRC and reports the errors or warnings, if any, in the CIW window. A successful DRC ensures that the layout passes through the rules designed for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. In our case, for an inverter, we really need a tool that can compare the connectivities of our layout with that of the schematic and ensure that it is really a layout for an inverter. One way 14

15 Cadence does this is by generating an Hspice netlist file from the layout and comparing it with the netlist for the schematic. This is the essence of the LVS tool. The first step is to extract all the connectivities and parasitic capacitances from your layout design. From the layout view window, choose Extract... under Verify menu. A window will pop-up. Make sure that the entries are as given below. For the entry in Switch Names, click on Set Switches. A window will pop-up. Choose the option for Extract parasitic caps. Finally, click on OK. The beauty of this extraction tool is that Cadence will recognize not only all the connections but also more importantly, if you have designed the layout correctly, it will also recognize all the nmos and pmos transistors. Your layout will then be extracted and while Cadence is doing so, the intermediary steps will be displayed in the CIW. It will tell you whether the extraction is successful or not. Open the extracted view of the cell from the Library Manager window. Press Shift-f to see the symbols for the active and passive devices appear in 15

16 the extraction view window. This is just symbolic to associate the portions of the layout with different devices. The extracted view will look something like this: The next step is to perform LVS. Since we generated a layout with certain a W and L for the transistors (for the case discussed here, both nmos and pmos W = 1.5u and L = 0.6u), the layout versus schematic operation will give you an error if the schematic against which the layout is compared has a different W and L for its pmos and nmos transistors. You need to make sure that Cadence is checking for certain LVS rules. To do so, click on NCSU 16

17 Modify LVS Rules from the layout view window of your inverter. A window should pop-up with a number of LVS options available for you to choose. For our purposes, you should verify that the following 4 items are selected: Allow FET Series Permutations, Combine Parallel FETs, Combine Parallel Capacitors, Compare FET Parameters. This check should be performed every time you are about to start an LVS. From the extracted layout window, choose Verify LVS. A pop-up menu will appear like below. If you already had an LVS directory, a window will pop-up which might say The selected LVS rule directory does not match the run form. Just select Form Contents and click OK. Run the LVS you can get the following result if it succeeds. 17

18 If there are any errors, click on Error Display in the LVS menu to view what went wrong. Click output from LVS window, you will see the following log file. It is very beneficial if you click on output window shown below. It will explain each of the terms in the above window in great detail. The si.log will also explain to you all the errors that it detected in both the schematic and layout views during the LVS comparison. One should realize that almost no one designs a perfect layout on the first attempt so do not expect to pass the LVS check on your first try. In most cases, there will be many errors reported by both the si.log file and the Error Display window. You should not be intimidated by all these errors. Many of these are, in fact, related to each other. Hence, once you fix one of these errors, many of the other errors should disappear. The idea is to concentrate on one error at a time, change the layout design accordingly and repeat the extraction and LVS steps until the layout and schematic views match perfectly with each other. (d) Using your test schematic created in 4(c), run a simulation of the analog extracted schematic generated from your layout to measure the dynamic per- 18

19 formance of your layout. The input should be created by passing the Vpulse from part 4(b) through your inverter from part 4(a). Your inverter should still be loaded with an identical inverter. Submit the test schematic, input/output transient waveforms, and your delay measurements (propagation and rise/fall times). Here are the instructions for post layout simulation. Open up the test schematic for the inverter. Select Launch ADE L. The same steps that you run simulation in previous homeworks. However, the one change that needs to be made is: goes to Setup Environment... and you will see the Environment Options window open up. Originally, the Switch View List should contain the following items: spectre cmos sch cmos.sch schematic veriloga In order for Cadence to simulate through the extracted view of the layout design instead of the schematic view, you will include an additional item (extracted) in the Switch View List such that it now contains the following: spectre cmos sch cmos.sch extracted schematic veriloga 19