Microelectronica. Full-Custom Design with Cadence Tutorial

Transcription

1 Área Científica de Electrónica Microelectronica Full-Custom Design with Cadence Tutorial AustriaMicroSystems C35B3 (HIT-Kit 3.70) Marcelino Santos

2 Table of contends 1. Starting Cadence... 3 Starting Cadence for the first time... 3 Starting Cadence again Creating the Schematic... 4 Creating a library and a schematic cell view... 4 Drawing the schematic... 5 Adding the MOS transistors... 5 Placing VDD and GND supply... 7 Adding input and output pins... 7 Adding wires and wire names... 7 Miscellaneous... 7 Saving the design Creating the Symbol Schematic Simulation... 9 Creating a test bench (schematic for simulation)... 9 Simulating the schematic Waveform Window Expressions Parametric analysis Creating the Layout Starting the layout tool Layer Selection Window (LSW) Initialize the layout Settings for the Virtuoso Layout XL Editor Layout creation - placing the components Routing between the components Layout creation - miscellaneous Design-Rule-Check (DRC) Starting DRC Processing DRC errors Extraction Starting extraction Layout-versus-Schematic Check (LVS Check) Starting LVS checking Analyzing LVS results Parasitics probing Post-Layout Simulation GDSII Export of the Cell Layout

3 Acknowledgements: The author thanks José Jesus and Sílvia Gomes for their precious help in the elaboration of this tutorial. 1. Starting Cadence Starting Cadence for the first time At first, open a terminal program and source the configuration file cad.init. > source cad.init Then create a directory for the project files and change to that directory. > mkdir cds_tutorial > cd cds_tutorial Then a script from AustriaMicroSystems is used to initialize the Cadence Custom IC Design tools with the process technology C35B3 (-tech c35b3). Also the Command Interpreter Window (CIW) is started in mode Front-To-Back Design (-mode fb). > ams_cds -mode fb -tech c35b3 After Cadence has been started two important windows appear: Command Interpreter Window (CIW): To start Cadence tools and enter SKILL commands. The output of the running tools are displayed here and closing this window causes the whole suite to close. Library Manager: To manage the cells with their various views in the libraries. Here new cells and libraries are created. This tool can be started from the CIW via the menu bar: Tools - Library Manager. Close the what s new windows and select the C35B3C0 process. The library manager window (Fig. 1) can be used for opening existing libraries or cells or creating new ones. The left column of the library manager window is a list of the current (accessible) libraries. Among these PRIMLIB contains the transistors you will need for the inverter. Left click at PRIMLIB. The middle column shows the elements of PRIMLIB. Left click at nmos4. This is the basic n-mos transistor. In the third, rightmost, column you can see several views of nmos4. You will need the symbol view for the schematic and the layout view for building the layout. 3

4 Starting Cadence again Fig. 1 Library Manager window If you want to start a new Cadence session in a directory where the Cadence tools have already been initialized only the following commands are necessary: > source cad.init > cd cds_tutorial > ams_cds -mode fb 2. Creating the Schematic Creating a library and a schematic cell view At first, a new library that will contain the data for the implemented cell must be created. From the menu bar of the Library Manager select File - New - Library and enter a name for the new library, e.g. STUDENTS. In the next window we choose to attach the library to an existing techfile. After pressing OK the techfile can be selected: Set Technology File to TECH_C35B3 and press OK. Now we can start to create the schematic of our cell. Select the newly made library and choose File - New - Cell View from the menu bar of the Library Manager. Enter a name for the cell in the appearing form (e.g. inverter1) and check whether the correct options are selected: Library Name must be set to STUDENTS, View Name must be set to schematic and Tool must be set to Composer- Schematic in order to start the Virtuoso Schematic Composer. After pressing OK the Schematic Composer should start automatically. 4

5 Drawing the schematic The following schematic is now entered into the Schematic Composer: Fig. 2 Schematic of the inverter. Before adding instances or wires in the inverter schematic, briefly read the Miscellaneous part in this section. Adding the MOS transistors First, add the pmos and nmos transistors. Select from the Composer menu bar Add - Instance (or use the shortcut <i>) Fill out the form by hand or press the Browse button to search the libraries for the appropriate cell. The MOS transistors are in the library PRIMLIB and are called pmos4 and nmos4 respectively. To place them in a schematic the selected View must be symbol. After choosing the right cell, parameters of the cell can be set in the form (Fig. 3). Change the default values of the transistor width (w pmos = 4 µm and w nmos = 1 µm) and place each symbol in the schematic using the left mouse button. 5

6 Fig.3 Dialogue box for the transistor properties. 6

7 To hide the Add Instance form during placing press the Hide button. To rotate or flip the cell press the Rotate (shortcut <r>), Sideways or Uside Down buttons. Placing VDD and GND supply Add instances of vdd and gnd supply cells which can be found in the library analoglib. Adding input and output pins To add input and output pins select Add - Pin (shortcut <p>) from the menu bar and fill out the appearing form. Give a list of Pin Names separated by spaces, e.g. IN OUT, and select the direction of the first pin in the list (IN is an input pin). Now place the first pin. To hide the Add Pin form, press the Hide button. To rotate or flip the pin press the Rotate (shortcut <r>), Sideways or Uside Down buttons. After placing the first pin its name is automatically deleted from the Pin Names list and the next pin direction can be changed and the pin placed. Place the input pin IN and the output pin OUT. Adding wires and wire names To add wires select Add - Wire (narrow) (shortcut <w>) from the menu bar and place wires by clicking on the begin and end point of a wire. Connect the objects via their connection ports. If the mouse pointer is moved near to a connection port and the port is marked with the diamond symbol the wire can be quick-connected to that port by pressing <s>. Don't forget to connect the bulk-ports of the pmos transistors with VDD and the bulkports of the nmos transistors with GND! To name a wire select Add - Wire Name (shortcut l) and fill in a list of wire Names in the appearing form. To hide the Add Wire Name form during naming press the Hide button. Add the wire names in the order as the appear on the Names list by clicking the appropriate wire. Note that wires given the same name are connected implicitly. The wires connected to the vdd cell are automatically named vdd! and the wires connected to the cell gnd are automatically named gnd!. Miscellaneous To zoom in on the schematic select Windows - Zoom - Zoom in (shortcut <z>) and drag a box around the area of interest. Alternatively, right click and draw the rectangle to zoom in. To fit the schematic window to the current design select Window - Fit (shortcut <f>). Very useful! To move an object: 7

8 Select the object and move the mouse pointer over it until the pointer changes to a move-object symbol. Press the left mouse button and move the object. Select Edit - Move (shortcut <M>) from the menu bar and select the object to move. To edit cell instance properties select the cell in the composer window and choose Edit - Properties - Objects (shortcut <q>) from the menu bar. In the Composer window you can see which command is currently activated and how many instances are currently selected. In the lower status bar you can see the current actions assigned to the mouse buttons according to the currently activated command. Very important! Multiple objects can be selected by: Holding down the <shift> key and selecting the objects. Draging a box around them with the mouse pointer while pressing the left mouse button. Other useful commands: command menu bar command shortcut copy object Edit - Copy <c> detele object Edit - Delete <DEL> rotate object Edit - Rotate <r> undo last action Edit - Undo <u> save the design Design - Save <S> move within window redraw window terminate any command <UP>, <DOWN>, <LEFT>, <RIGHT> <F6> <ESC> Very useful! Saving the design Save the design by choosing Design - Check and Save (shortcut <X>) from the menu bar. Possible errors are indicated by flashing markers. These markers can be deleted by selecting Check - Delete All Markers and pressing OK. 3. Creating the Symbol Creating a symbol of the cell is necessary if the cell should be instantiated in another schematic (i.e. the simulation schematic). The symbol defines the shape your cell will assume in another schematic. To create the symbol, open the cell schematic in the Virtuoso Composer and select Design - Create Cellview - From Cellview and check whether the appearing form is filled in correctly: To View Name must be set to symbol and Tool / Data Type must be set to Composer-Symbol. After hitting OK the form 8

9 Symbol Generation Options appear where the initial positions of the pins can be chosen. Press OK after assigning the pins to the desired lists. The Virtuoso Schematic Composer will open in symbol-editing mode and a default symbol will be created for the cell. Now the symbol can be designed. After finishing the design of the symbol check and save it with: Design - Check and Save. The final symbol could look like this (click on the picture to enlarge it): Fig.4 Inverter symbol. After finishing the design of the symbol check and save it with: Design - Check and Save. 4. Schematic Simulation Creating a test bench (schematic for simulation) The first step to simulate the inverter is to create a schematic with an instance of the new inverter1 (symbol). To create a schematic refer to section 2. Creating the Schematic of this document. The schematic of the test bench must be created in the library STUDENTS and the cell should be named inv_test. The inverter gate in the simulation schematic is of course the cell inverter1 from the library STUDENTS. 9

10 Add a instance (<i>) of a DC voltage source between vdd and gnd. Use the cell vdc from the library analoglib and set the parameter DC Voltage to vdd_val V. By connecting this voltage source to the cells vdd and gnd, from the library analoglib, you are defining vdd and gnd for all the cells that use these labels. V Fig.5 vdc instance with parametric DC voltage In order to generate the input signal for the simulation use a voltage source of type vpulse (rectangular signal) from the library analoglib. Define the voltage source with the following parameters: 10

11 Voltage 1 Voltage 2 vpulse voltage source at input IN 3.3 V 0.0 V Delay time 0 s Rise time Fall time Pulse width Period 5n s 5n s 45n s 100n s Note that all parameters in the previous table can be defined as function of parameters (e.g. Pulse with = input_slew; Pulse with = 50n-input_slew). These parameters must be assigned in the simulator environment, with a constant value or in a parametric analysis. We also have to name the input wire (e.g. IN) and the output wire (e.g. OUT) so that we can select them during simulation and plot their voltage curves. Add a capacitor (cap) of 1pF to the output pin from the library analoglib. You should end up with the test bench of Fig. 6. vdc = vdd_value Fig. 6 Test bench for the inverter transient simulation. Simulating the schematic After creating the simulation schematic you are ready to simulate the inverter gate. Select from the Composer window of the simulation schematic Tools - Analog Environment 11

12 The following simulator settings have to be made: menu bar command Setup - Simulator/Directory/Host details - Set Simulator to spectres - Also the Project Directory could be changed here - Check the model library files. In some cases the library Setup - Model Path /soft/ams/3.7/spectres/cmos53/tm is referred as cmos15/tm. Double click the library to change, edit and select the CHANGE button. Setup - Temperature - Set Degrees to 25 Setup - Environment Analyses - Choose Variables - Copy From Cellview Outputs - To Be Plotted - Select On Schematic - Switch View List should be set to spectres cmos_sch schematic - Stop View List should be set to spectres ahdl - Set Analysis to trans - Set Stop Time to 200n - Accuracy Defaults should be set to conservative - A description of the analysis will be listed in the field Analyses of the Virtuoso Analog Environment tool - To edit the Analyses entries either double-click on an entry or select Analyses Choose again - Variables in the simulation schematic will be identified and will be listed in the field Design Variables of the Virtuoso Analog Environment tool - To edit the Design Variables entries either double-click on an entry or select Variables - Edit from the menu bar - Set vdd_val to 3.3V - Select the signals to be ploted in the simulation schematic: net (must be named!) => voltage; object node => current into the object through this node - Selected signals will be listed in the field Outputs of the Virtuoso Analog Environment tool - To edit the Outputs entries either double-click on an entry or select Outputs - Setup from the menu bar After configuring the simulator it should look like Fig. 7. Fig. 7 Simulation configuration window. 12

13 To build the netlist and run the simulation select Simulation - Netlist and Run. First the simulator output log window appears and shows the simulation progress. After the simulation has finished the waveform window appears and the selected signals are plotted. Waveform Window Fig. 8 Simulation waveform window. In order to perform arithmetic operations you can use the calculator: Tools calculator In the IO area of the calculator window (see Fig. 9) you can type the expression to evaluate (see the list of functions presented) and see the result after clicking eval. 13

14 IO area Fig. 9 Calculator window. Expressions It is also possible to enter expressions in the field Outputs of the Virtuoso Analog Environment to calculate parameters of the cell (propagation delay, output slew,...) from the simulation results directly or to plot modified signal curves. These expressions can be tested with the Calculator! Select Outputs - Setup from the menu bar of the Virtuoso Analog Environment and add the following expression: Name = propagation delay, Expression = delay(v("/in"?result "tran") "rising" v("/out"?result "tran") "falling") The expression propagation delay gives the propagation delay of the gate when the input value changes from IN = 0 to IN = 1. Fig. 10 Adding an expression to be evaluated or displayed. 14

15 After plotting the expression with Results - Plot Outputs - Expressions the result of the expression for the propagation delay is displayed in the field Outputs of the Virtuoso Analog Environment. The current curve of an object node can be accessed with the command i("/object/node"?result "tran"). Fig. 11 Expression value display in the Virtuoso Analog Environment. Parametric analysis It is very important to evaluate the circuit behaviour with different temperatures, supply voltages and technological parameters. Parametric analysis is used in this tutorial to sweep the vdd_val parameter and the temperature. In the Virtuoso Analog Environment select Tools Parametric Analysis Fig. 12 Parametric analysis window. 15

16 In the Parametric analysis window select Setup Pick Name for Variable sweep 1 and select temp. In the Parametric analysis window assign: and select Analysis Start Field Step Control From -10 To 50 Value Linear Steps Step Size 10 Range Type From/To Fig. 13 Parametric analysis display in the waveform window (with a 1-> 0 zoom in). Fig. 13 shows how results of parametric analysis with expressions are displayed in the waveform window: a new graph is displayed with the expression result evolution. In order to change the power supply value, in the Parametric analysis window select Setup Pick Name for Variable sweep 1 and select vdd_val. In the Parametric analysis window assign: Field Step Control From 2 To 4 Value Linear Steps Step Size 1 Range Type From/To and, once again, select Analysis Start. 16

17 5. Creating the Layout Starting the layout tool Open the schematic view of the inverter1 cell and select Tools - Design Synthesis - Layout XL from the menu bar. Selecting this option will first open a small dialog box that will let the user create a new layout or open an existing one. We opt for Create New. The next dialog gives us the possibility to change the properties of the new cellview. Check whether the View Name is set to layout and the Tool is set to Virtuoso. After pressing OK the Virtuoso Layout XL Editor will start. Layer Selection Window (LSW) Also the Layer Selection Window (LSW) is started (Fig.14). Each LSW entry is divided in three categories which are color, abbreviated name and purpose. Color shows the appearance of the layer in the layout. The abbreviation is the official name of the layer for Virtuoso, it can appear in messages, etc. The Layer Selection Window is used to select the active layer (left mouse-button), to set whether a layer is selectable or not (right mouse-button) and to set whether a layer is visible or not (middle mouse-button). After the visibility status of a layer has been changed press the <F6> key to refresh the screen. Each layer appears in the LSW window with purpose drw for drawing and pin for pin, you will almost always need drw. Initialize the layout To initialize the layout according to the schematic (i/o pins, device instances,...) select Design - Generate From Source in the Virtuoso Layout XL Editor menu bar. Fill out the appearing form to set some properties of the components in the layout: set the boundary width to 3 µm and the boundary height to 13 µm. Compare the other fields of the form with Fig 15. Fig.14 LSW Check the Pin Label Shape = Label box and enter the Pin Label Options dialogue window. Set the Layer Name and Layer Purpose to Same as Pin. 17

18 Fig.15 Layout generation options. After hitting OK the Virtuoso Layout XL Editor creates the chosen components in the layout window (Fig. 16). 18

19 Fig.16 Layout automatically generated based on the schematic. Settings for the Virtuoso Layout XL Editor Select Options - Display and, in the new opened window, assign X Snap Spacing and Y Snap Spacing to 0.025, and Display Levels: From = 0, To = 2. Useful commands are: command menu bar command shortcut save the layout Design - Save <F2> zoom in Window - Zoom - In <z> fit complete layout in the layout window Window - Fit All <f> redraw layout window Window - Redraw <F6> create ruler Window - Create Ruler <k> delete all rulers Window - Clear All Rulers <K> undo last action Edit - Undo <u> move object Edit - Move <m> stretch object Edit - Stretch <s> delete object Edit - Delete <DEL> edit object properties Edit - Properties <q> terminate any command <ESC> Very useful! 19

20 Layout creation - placing the components A first placement iteration can be obtained by selecting Edit Place as in Schematic The replaced cells will look like Fig. 17. At this stage, in more complex cells, the commands Connectivity show incomplete nets / hide incomplete nets may be of interest. prboundary = limits of the cell layout Fig. 17 Layout after Place as in schematic command. When a pin or MOS transistor is selected in the Layout Window, the corresponding device is also highlighted in the Schematic Window. This works also when a component is selected in the Schematic Window. When the Drain or Source contacts of two similar transistors are connected directly, Virtuoso XL will chain these transistors automatically after shifting the according areas over each other. Furthermore Virtuoso XL determines the necessity for an additional connection to this area. To rotate a transistor either select the command Edit - Move, select the transistor you want to rotate and press the right mouse button or bring up the object properties of the appropriate transistor and change the entry Rotation (Fig.18). 20

21 Fig. 18 Transistor properties including Rotation = 90º. While a command is activated its detailed behavior can be customized by pressing the <F3> key (e.g. set snap mode). Very useful is Virtuoso XL's status bar just above the menu bar: X: and Y: indicate the actual mouse pointer's position. The letter enclosed by parenthesis indicates whether partial selection mode (P) or full selection mode (F) is activated. Toggle between these two settings by pressing <F4>. The Select: entry shows how many objects are currently selected. When moving components, dx:, dy: and Dist: show the difference between starting point and end point. In the Cmd: field one can determine the currently active command. Also very useful is the mouse function indicator at the bottom of the Layout Window. There the currently assigned functions to the mouse buttons according to the active command are indicated. Gnd and vdd rectangles Zoom in the bottom of the prboundary (<z>). Select the layer metal 1(MET1) of type drawing (drw), clicking in the corresponding layer in the LSW (see Fig.14). Draw a ruler (<k>) from coordinates (0, 0) to (0, 1.8). Starting at coordinates (0, 0), draw a rectangle (<r>) of metal 1 with the total width of the prboundary (that will be the limit of the cell) and 1.8 µm of height (see Fig. 19). 21

22 Fig. 19 Gnd rectangle in metal1. Copy this metal 1 rectangle to the top of the prboundary box (for vdd usage). Place the gnd pin and label over the metal 1 rectangle in the bottom of the cell. For simulation purpose it can be placed anywhere. If the cell would be used in an automatic placement and routing process, two rectangles of metal 1 of type pin should be overlapped to the metal 1 drw, at each access of the ground rectangle. Each metal 1 pin rectangle points to an access to the net and therefore its properties must include the directions from where the access is allowed (Fig.20). Place the vdd pin and label over the metal 1 rectangle in the top of the cell. The placement of the global pins gnd! and vdd! needs some additional setting. Their properties have to be additionally edited. After selecting them and depressing <q> the Edit Instance Properties dialog box opens. Here Connectivity has to be checked. Terminal Name is displayed (gnd! or vdd!). Net Expression Property and its Default value has to be defined as gnd and gnd! as well as vdd and vdd! respectively. If this property is missing then everything will run correctly with the only exception of the simulation of the extracted netlist. The LVS will not be influenced, but the simulator will not be able to connect the power supply to the power rails of the layout and, therefore, the circuit will not function at all. 22

23 Fig. 20 Assigning access directions to a pin. Substrate and n-well connection In order to connect the ground metal 1 rectangle to the substrate a contact can be automatically generated selecting: Create Contact and selecting PD_C. Place the bottom-left corner of the contact at coordinates (0, 0). This contact includes the active area (diff), p+select (pplus), metal 1 (met1), and the contact (cont). It performs a good ohmic contact between metal 1 and the substrate. In order to connect the n-well to vdd, the n-well included in the pmos transistor must be extended to include the vdd line. Select the layer NTUB of type drawing and draw a rectangle starting from the top of the pmos n-well and ending 0.9 µm above the vdd line. (see Fig. 24). Similarly to the gnd contact to substrate, select the ND_C and place the top-left corner of the contact at coordinates (0, 13). This contact includes the active area (diff), n+select (nplus), metal 1 (met1), and the contact (cont). It performs a good ohmic contact between metal 1 and n-well (see Fig. 24). Placing the transistors Create a ruler (<k>), starting from the top of the gnd rectangle, with 0.45 µm of lenght. Rotate (see item Layout creation placing the components in this section) and move (<m>) the nmos transistor, centring in the prboundary box and bringing the metal 1 drain and source to the distance pointed by the ruler (see Fig. 21). 23

24 Fig. 21 Gnd rectangle with pin assignment, substrate connection and nmos placement. Create a ruler (<k>), starting from the top of the nplus of the nmos transistor, with 1.2 µm of lenght (see Fig. 22). Rotate and move (<m>) the pmos transistor, centring in the prboundary box and bringing the nwell (ntub see Fig. 22) to the distance pointed by the ruler. 24

25 Fig. 22 pmos placement. Routing between the components The next step in layout creation is to connect the components electrically according to the schematic. Connections can be drawn in three different ways: type of connection menu bar command shortcut rectangle Create - Rectangle <r> polygon Create - Polygon <P> path Create - Path <p> Before activating a command select the desired layer in the Layer Selection Window (LSW)! When the path command is activated and the path has been started at an identifiable connection Virtuoso XL highlights the geometries and terminals of other components which should be connected. To change the layer while drawing a path use the path options invoked by pressing <F3>. There the Change To Layer option can be modified and Virtuoso XL automatically generates the contacts from one layer to another. Inter-layer contacts can be created explicitly through Create - Contact (shortcut <o>). To establish a connection between the metal layer 2 and the poly layer 1, two of these contacts 25

26 have to be placed: MET2 -> MET1 (VIA1_C) and MET1 -> POLY1 (P1_C). They can be placed right over each other. With the command Connectivity - Show Incomplete Nets one can highligt signal nets that haven't been routed correctly and completely. To end the highlighting of incomplete nets select Connectivity - Hide Incomplete Nets from the menu bar. Fig. 23 Gates and drains interconnection. Fig. 23 shows the gates and drains interconnections and the OUT pin placement over the corresponding metal 1 connection. Fig. 23 also shows a poly-metal 1 contact that allows connectivity in metal 1 to the input of the inverter (Create Contact P1_C). The sources of the transistors must be connected to vdd! and gnd! (see Fig. 24). The IN pin and label must be moved to the top of the metal 1 connected to the inverter input (overlapping the P1_C contact, not displayed in Fig. 23 for clarity). 26

27 Fig. 24 Connection of the pmos source, n-well contact and vdd! pin assignment. Layout creation - miscellaneous While placing components and routing, periodically start the Design-Rule-Check (DRC) in order to identify any violations of the design rules of the current process technology (min. spacing between geometries, min. width of geometries,...). When implementing a standard cell it is also very important to consider the distances of geometries on the various layers to geometries in adjacent placed cells. These errors can't be found by the DRC of the single cell. The DRC will be explained in detail in the next section. If the schematic of the cell is changed during or after the layout of the cell has been designed, the following commands could be of interest: command change the nets at the terminals of an instance update of components and nets menu bar command Connectivity - Propagate Nets Connectivity - Update - Components And Nets 27

28 6. Design-Rule-Check (DRC) The layout of a cell must be drawn according to a set of strict design rules. During the Design- Rule-Check a program checks the design against the design rules and reports any violations. Starting DRC To start the DRC for the layout select Verify - DRC from the menu bar of the Virtuoso Layout XL Editor where the layout intended for checking is opened. In the appearing form, the DRC can be parameterized. Set the following options: Checking Method option set to comment Checking Limit flat full any instances of other cells found in the layout should also be checked (layout of this cells must also be available!) Switch Names... to set additional options for the DRC e.g. to ignore some rules Rules File../divaDRC.rul design rules file name Rules Library TECH_C35B3 Disable the library that contains the design rules file Fig. 25 DRC options. 28

29 After hitting OK the DRC is carried out and any violations are highlighted in the layout by flashing markers and the errors are reported in the CIW (see Fig. 26). Processing DRC errors Fig. 26 CIW DRC errors. To get a complete list of all errors select HIT-Kit utilities - Find DRC Markers Only the errors listed in Fig. 27 should be identified by the DRC of the inverter. Fig. 27 Expected errors in the inverter. They could easily be avoided when we set the switch no_coverage in the DRC options form. These errors (Minimum... density...) only make sense in the scope of the whole layout of the chip where they must be treated as severe errors. Generally, if you neglect a DRC error you should really be able to explain why this error can be ignored. 29

30 When we select an error in the list, Virtuoso XL focuses to the area in the layout where the error occurs. If there is more than one error with the same name, we can switch between these errors with the Error Number slider. The Zoom Factor applied by Virtuoso XL to focus to an error can also be set with a slider. To delete all markers press the button Delete all Marker in the DRC Error Search form or select Verify - Markers - Delete All from the Virtuoso XL menu bar. Some c35b3 rules are: Minimal: Width Spacing NTUB 3 3 DIFF 0,3 0,6 POLY1 0,35 0,45 PPLUS/NPLUS 1,6 1,6 POLY2 0,65 0,5 CONT 1 1,2 MET1 0,5 0,45* VIA 1,2 1,6 MET2 0,6 0,5** PAD * If the MET1 is wide (width>10µm) then 0,8 ** If the MET2 is wide (width >10µm) then 0,8 Width Spacing Minimum spacing between different layers: DIFF PPLUS 0,35 CONT in MET1 POLY1 0,8 CONT in POLY2 POLY1 1,6 POLY1 VIA 1 POLY2 VIA 1,2 CONT VIA1,2 POLY1 POLY2 1,4 POLY1 DIFF 0,4 POLY2 DIFF 1,2 Overhang in transistors: POLY1 over DIFF 0,6 DIFF over POLY1 1,4 Spacing inside the surrounding layer (overlap) VIA in MET1 0,2 VIA in MET2 0,3 NDIFF in NTUB 0,2 DIFF in NPLUS 0,45 DIFF in PPLUS 0,45 30

31 7. Extraction Circuit extraction is performed after the mask layout design of the cell is completed. It creates a detailed netlist (extracted netlist) of the cell which can be used for example in the Layoutversus-Schematic check or by a circuit simulator. The circuit extractor is capable of identifying the individual transistors and their interconnections as well as the parasitic resistances and capacitances that are inevitably present in the cell. Thus, the extracted netlist provides a very accurate model of the cell. Starting extraction To start the extraction select Verify - Extract from the menu bar of the Virtuoso Layout XL Editor where the layout intended for extraction is opened. In the appearing form, the options for the extractor can be given. Set the following options: option set to comment Extract Method Switch Names flat capall View Names Extracted extracted Rules File../divaEXT.rul extraction rules file name Rules Library any instances of other cells found in the layout should also be extracted (layout of this cells must also be available!) to set additional options for the extraction process e.g. capall tells the extractor to additionally extract parasitic capacitances TECH_C35B3 Disable the library that contains the extraction rules file After hitting OK the extraction is carried out and a new view called extracted is generated for the cell (Library Manager). 8. Layout-versus-Schematic Check (LVS Check) After the mask layout design of the cell is completed, it should be checked against the schematic of the cell created earlier. The Layout-versus-Schematic check (LVS check) will compare the circuit given by the schematic with that one extracted from the mask layout and tries to prove that both networks are equivalent. The LVS step provides an additional level of confidence for the integrity of the design and ensures that the mask layout is a correct realization of the intended circuit. Note that the LVS check only guarantees topological match: A successful LVS check will not guarantee that the mask layout of the cell will actually satisfy the performance requirements. Any errors that may show up during the LVS check (such as unintended connections between transistors, missing connections/devices,...) should be corrected in the mask layout. Note that the extraction step must be repeated every time the layout of the cell is modified. 31

32 Starting LVS checking To start the LVS check select Verify - LVS from the menu bar of the Virtuoso Layout Editor where the extracted netlist of the cell intended for LVS checking is opened. If a form called "LVS Form Contents Different" appears, select Use: Form Contents and press OK. In the next form, the options for the LVS check can be set: It can be specified which cell views should be compared and where to find the LVS rules file. Fill out the form as Fig. 28. After clicking Run the LVS check is started. Analyzing LVS results Fig. 28 LVS options. When the LVS check is finished, a window appears that indicates whether the check was successful or not. To view the LVS check results in detail, press the Output button in the LVS Window. The file si.out in the given working directory contains the LVS check results. For further information (LVS run log file, schematic/extracted netlist,...) press the Info button. 32

33 Fig. 29 LVS result. Parasitics probing The different nets in the extracted netlist can be probed to get a summary of the parasitics (resistances, capacitances) present on the nets. Since we could only extract parasitic capacitances during the extraction of the netlist, no values for parasitic resistances are indicated. To set a parasitics probe press the button Parasitic Probe in the LVS Window. In the next window press the button Whole Net and select a net in the layout window where the extracted view is shown. It is also possible to get a summary of parasitics between nets. Therefore, use the button Net To Net before selecting two nets in the extracted view. 33

34 9. Post-Layout Simulation It is now easy to simulate the layout (more exactly the extracted netlist) with the Virtuoso Analog Circuit Design Environment. Close the layout editor window and open the test bench for the simulation of the cell schematic (Section 4. Schematic Simulation). The same test bench can be used for the extracted simulation. Open the test bench schematic and select from the Composer window of the simulation schematic Tools - Analog Environment Configure the simulation conditions as described in Section 4 and choose: Setup - Environment and set Switch View List to spectres cmos_sch extracted schematic. As a result of this, if the simulator now creates the netlist of the simulated circuit it uses the extracted netlist of the cell rather than the schematic. 10. GDSII Export of the Cell Layout To export the mask layout of the cell in GDSII format select the following command in the CIW: File - Export - Stream. Fill out the appearing form like depicted below: 34

35 Fig. 30 GDSII export. Note that the run directory gds2export must be created in the current directory cds_tutorial before the export can be started. The log file of the export process (PIPO.LOG), which explains warnings and errors during export in detail, and the GDS2-file itself will be stored in the run directory. The Layer Map Table, which can be stated by pressing the button User-Defined Data, should be set to /soft/ams/artist/hk_c35/tech_c35b3/strminout.layertable There are two warnings given for the export process concerning the layers (changedlayer 220 tool0) and (prboundary 235 drawing). These warnings can be safely ignored. 35