Anand Raghunathan

Transcription

1 ECE 695R: SYSTEM-ON-CHIP DESIGN Module 2: HW/SW Partitioning Lecture 2.15: ASIP: Approaches to Design Anand Raghunathan ECE 695R: System-on-Chip Design, Fall 2014 Fall 2014, ME 1052, T Th 12:00PM-1:15PM 2014 Anand Raghunathan 1

2 Approaches to ASIP Design Design from scratch Design from a base architecture Application Design ISA and micro-architecture from scratch ASIP Application Register File LD/ST ALU MUL FU User-Defined Execution Units LD/ST Register File ALU MUL FU Customize base architecture Memory User-Defined Register File ASIP Memory Base Architecture ECE 695R: System-on-Chip Design, Fall

3 ECE 695R: System-on-Chip Design, Fall Approaches to ASIP Design: Design from Scratch Example LISATek (TU Aachen / Co-Ware / Synopsys) Key technology: Processor description language to specify ISA + microarchitecture

4 ECE 695R: System-on-Chip Design, Fall Approaches to ASIP Design: Design from Scratch Example LISATek (TU Aachen / Co-Ware) Key technology: Automatic generation of HW (RTL)

5 ECE 695R: System-on-Chip Design, Fall Approaches to ASIP Design: Design from Scratch Example LISATek (TU Aachen / Co-Ware) Key technology: Automatic generation of SW tool chain

6 Approaches to ASIP Design: Design from a Base Architecture Micro-architecture configuration Tune various parameters that affect performance and hardware complexity, not the ISA Instruction Set Sub-setting Use only the sub-set of the base ISA that a given application needs Instruction-set Extension Extend the base ISA by adding custom instructions ECE 695R: System-on-Chip Design, Fall

7 ECE 695R: System-on-Chip Design, Fall Micro-architecture Configuration Typical Parameters: Reg. file size, cache size & associativity, local memories, load/store buffers, interfaces, Configuration Example: Xtensa from Tensilica Instruction Fetch / Decode Base ISA Execution Pipeline Register File Base ALU Optional Execution Units Processor Controls Trace/TJAG/OCD Interrupts, Breakpoints, Timers Local Instruction Memories External Bus Interface Processor Interface (PIF) to System Bus Base ISA Feature Configurable Functions Optional Function Optional & Configurable Load/Store Unit #2 Vectra LX DSP Engine Data Load/Store Unit Local Data Memories Xtensa Local Memory Interface

8 ISA Sub-setting: Motivation Applications do not use complete ISA! 100% 75% 50% 25% 0% bubble_sort crc Percent of ISA Used des fft fir quant iquant turbo vlc bitcnts CRC32 qsort sha stringsearch FFT dijkstra patricia gol dct dhry AVERAGE Potential for hardware (area, power) reduction ECE 695R: System-on-Chip Design, Fall 2014 Source: Yiannacouras et al., U. Toronto 8

9 ECE 695R: System-on-Chip Design, Fall 2014 ISA Sub-setting Simplify processor HW by reducing the ISA Fraction of Area Automatically eliminate unused components and connections during HW generation bubble_sort crc des fft fir quant iquant turbo vlc bitcnts CRC32 qsort Benchmark Area reduced by 60% in some cases, 23% on average Similar reductions for energy, small impact on performance sha stringsearch FFT_MI dijkstra patricia gol dct dhry AVERAGE 23% Source: Yiannacouras et al., U. Toronto 9

10 ECE 695R: System-on-Chip Design, Fall ISA Extension Design custom instructions and corresponding HW that fits into processor pipeline Configuration Example: Xtensa from Tensilica Instruction Set Extension User Defined Queues / Ports up to 1M Pins Base ISA Feature Configurable Functions Optional Function Optional & Configurable Designer Defined Features (TIE) Instruction Fetch / Decode Designer-defined FLIX parallel execution pipelines - N wide User Defined Execution Units, Register Files and Interfaces Load/Store Unit #2 User Defined Execution Units, Register Files and Interfaces Base ISA Execution Pipeline Register File Base ALU Optional Execution Units User Defined Execution Unit Vectra LX DSP Engine Data Load/Store Unit Processor Controls Trace/TJAG/OCD Interrupts, Breakpoints, Timers Local Instruction Memories External Bus Interface Local Data Memories Xtensa Local Memory Interface Processor Interface (PIF) to System Bus

11 ECE 695R: System-on-Chip Design, Fall Simple Example (Nios) t 1 = a * b; t 2 = b * 0xf0; ; t 3 = c * 0x12; t 4 = t 1 + t 2 ; t 5 = t 2 + t 3 ; t 6 = t 5 + t 4 ; a b c 0xf0 extop1 t 1 = extop1(a, b, 0xf0); t 2 = extop2(b, c, 0xf0, 0x12); t 3 = t 1 + t 2 ; * * * x12 extop2 *: 2 clock cycles +: 1 clock cycles Execution time: 59 clock cycles Speedup: 1.8 Extended Instruction Set: I extop1 expop2

12 Complex Example: Collapse a subset of the instructions in a basic block into a single instruction Exploit the parallelism within the basic block Simplify operations with constant operands Optimize sequences of instructions (logic, arithmetic, etc.) Exploit limited precision ECE 695R: System-on-Chip Design, Fall 2014 K. Atasu, L. Pozzi, P. Ienne, DAC 03 12

13 Benefits of Configurability and Extensibility Consumer Electronics DSP Networking Extensible optimized Extensible out-of-box MIPS64 20Kc ARM1020E MIPS64b (NEC VR5000) MIPS32b (NEC VR4122) ConsumerMarks/MHz TeleMarks/MHz NetMarks/MHz Source: EEMBC Benchmark Consortium Copyright 2009, Grant Martin

14 ASIP impact on energy consumption Application Reference Processor Optimized Processor Energy Improvement Dot-Product Area (mm2) Cycles (K) Power (mw/mhz) Energy (µj) x AES Area (mm2) Cycles (K) Power (mw/mhz) Energy (µj) x Viterbi Area (mm2) Cycles (K) Power (mw/mhz) Energy (µj) x FFT Area (mm2) Cycles (K) Power (mw/mhz) Energy (µj) x Copyright 2009, Grant Martin. 14

15 Extensible Processor Tool Flow Tensilica Tool Flow Hardware + GUI-Based Specification of Coarsegrained configuration parameters PDL-Based Specificaion of instruction extensions Processor Generation Tools and Process Software Tool Chain Estimation of QoR ECE 695R: System-on-Chip Design, Fall 2014 Manual iteration 15

16 Summary ASIPs are a promising candidate to become a building block for future complex SoCs Replace hardwired processing units with programmable versions Sea of processors Two basic approaches to ASIP design From scratch Key technology: Architectural Description Language + automatic generation of full processor HW + re-targetable SW tool-chain From base architecture ISA sub-setting or extension Key technology: Instruction description language + automatic generation of custom instruction HW + re-targetable SW toolchain Easier to design and automate due to more constrained nature of changes ECE 695R: System-on-Chip Design, Fall