OUTLINE. System-on-Chip Design ( ) System-on-Chip Design for Embedded Systems ( ) WHAT IS A SYSTEM-ON-CHIP?

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1 September 3, 2018 System-on-Chip Design ( ) System-on-Chip Design for Embedded Systems ( ) 2 OUTLINE Short general introduction to IC design Organization of this course 3 WHAT IS A SYSTEM-ON-CHIP? A single chip that contains a complete electronic system. It usually contains a microprocessor, other digital hardware, software, and mixed-signal (I/O) functions. 4 WHY VERY LARGE SCALE INTEGRATION (VLSI)? Integration improves the design: lower parasitics = higher speed; lower power; physically smaller. Integration reduces manufacturing cost: (almost) no manual assembly. Note: some of the slide material for this presentation has been taken from the slides belonging to: Wolf, W., Modern VLSI Design, System-on-Chip Design, Third Edition, Prentice Hall PTR, Upper Saddle River, New Jersey, (2002).

2 5 EXAMPLE: SC14480 (Single-Chip DECT) PLL 165MHz TIMER PCM LDO LDO LDO AFE SDI 8/16/32 KHz Codec Class-D + filters White LED Vbat x3 CR16C+ 40 MHz Gen2DSP 80 MHz DSP ROM + 2kB RAM 24 kbyte RAM 5 Mb Flash DIP RAM DIP DMA GPIO SPI UART ACCESS 10 bit ADC RF part 6 MOORE S LAW Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Next pages show the evolution of the transistor count for processors (source: Wikipedia, entry: transistor count ). 7 MOORE S LAW GRAPH 8 TRANSISTOR-COUNT EVOLUTION (1) 7 Processor Transistor count Year Process Intel , µm Intel , µm Intel , µm Intel , µm Intel , µm Intel , µm Intel ,180, µm Pentium 3,100, µm

3 9 TRANSISTOR-COUNT EVOLUTION (2) Processor Transistor count Year Process Pentium III 9,500, µm Pentium 4 42,000, nm AMD K8 105,900, nm Cell 241,000, nm POWER6 (IBM) 789,000, nm Six-Core Core i7 1,170,000, nm Quad-Core z196 (IBM) 1,400,000, nm Quad-Core Itanium Tukwila 2,000,000, nm 8-Core Xeon Nehalem-EX 2,300,000, nm 10-Core Xeon Westmere-EX 2,600,000, nm 10 TRANSISTOR-COUNT EVOLUTION (3) 11 TRANSISTOR COUNTS OF SOME OTHER RECENT ICS GPUs (graphics processing units): AMD Vega, 2017: transistors, 14 nm process Nvidia GP100 Volta, 2017: transistors, 12 nm process FPGAs (field-programmable gate arrays): Intel/Altera Stratix 1010GX5500/10SX5500, FPGA, 2017: transistors, 14 nm process Xilinx Everest FPGA/DSP, announced for 2018: transistors, 7 nm process. 12 COST FACTORS IN ICs (180 nm TECHNOLOGY) Recurrent costs: silicon area (about 0.07 $/mm 2 ) packaging (0.1 up to several dollars) testing (about 0.05 $/sec) Typical IC: 10 to 100 mm 2, 1 to 10 seconds of test time. Non-recurrent costs: design time (about 100 $/hour/engineer) mask sets (in the order of 100 k$ per set) It often happens that silicon is not first time right new mask sets per redesign.

4 13 14 TECHNOLOGY TRENDS MASK-SET COSTS Established technologies such as 180 nm are relatively cheap. Technology roughly takes steps of 2: 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 14 nm, 10 nm, 7 nm State-of-the-art 2018:7 nm production taking off. Example: Apple A12 processor Mask-set costs rise above 1 M$ (see next slide): First-time right becomes even more important Requires advanced verification methods Source: retrieved September 3, THE SoC DESIGN PROCESS Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics. Test vectors for testing. FPGA prototyping (of digital subsystem). Application software. CHALLENGES IN VLSI DESIGN Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant.

5 17 DEALING WITH COMPLEXITY (1) Divide-and-conquer: limit the number of components you deal with at any one time. Group several components into larger components: transistors form gates; gates form functional units; functional units form processing elements; etc. 18 DEALING WITH COMPLEXITY (2) abstract concrete 19 DESIGN VERIFICATION Must check at every step that errors haven t been introduced; the longer an error remains, the more expensive it becomes to remove it. Forward checking: more detailed design should behave as less detailed version. Back annotation: transport performance numbers from more detailed to less detailed descriptions. 20 MANUFACTURING TEST Not the same as design verification: just because the design is right doesn t mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade.

6 21 COURSE CONTENTS Course aims at offering a representative look into system-onchip design. Bachelor curriculum already contains quite some analog electronics start here at a more advanced level. Digital design starts at rather a basic level. Design tools are crucial to cope with complexity. This course will let you work with several state-of-the-art professional tools, mostly obtained through Europractice. 22 EWI Groups and Staff Course breakdown Course materials Student teams Grading ORGANIZATION 23 RESPONSIBLE GROUPS AND STAFF Computer Architecture for Embedded Systems Floor 5 of Zilverling Building. INSTRUCTOR: Dr.ir. Sabih H. Gerez 1) ASSISTANTS: Anuradha Ranasinghe, M.Sc. Arvid van den Brink, M.Sc. (backup only) TECHNICAL SUPPORT: Bert Helthuis Integrated Circuit Design (EWI-ICD) INSTRUCTOR: Dr.ir. Ronan van der Zee ASSISTANTS: to be announced. 1) One day per week at the University of Twente; otherwise running company Bibix ( weeks per quarter SoC Design: 2 quarters SoC Design for ES: 1 quarter STUDY LOAD Study load concentrated on first 8 weeks of quarter 5 ECTS = 140 hours per quarter 140/8 = 17.5 hours per week of which 16 scheduled So 1.5 hours of homework per week Of course, students are not equal; some may need more and some less than nominal load.

7 25 26 COURSE STRUCTURE Week Week HDL-Based SoC + ES Integration by CAES AMS by ICD Final Integration by CAES + ICD STUDENT TEAMS Teams of 2 for HDL-Based Design and Mixed-Signal Design (or teams of 1 in case of odd number of students) You are free to choose your partner. In case of collaboration difficulties (e.g. asymmetric contributions) report to assistants or lecturer as soon as possible. Groups administered in Canvas (try self sign-up). One large team for 7-week Final Integration Project of SoC Design (team size 10 to 15 students; two teams in case of more participants) Teams of 2 for 3-week Integration Project of SoC for ES INTEGRATION PROJECT Apply the knowledge of the modules in a large-scale design. Organized as an industrial project. Student results of previous years are in principle available. Design for: : FM software radio : Electronic Bat (multi-beam acoustic imaging) : Audio pen : Beamforming Receiver (RF 433 MHz) : Meeting-room microphone with speaker detection : RF transceiver system for audio streaming. Prototyping on an Altera Cyclone FPGA board (for digital circuitry) and discrete analog components. Simulation model for SoC realization. COURSE MATERIAL Canvas: All information on the course, including study material will be on-line, accessible through the course s Canvas page. All students must register via Osiris! SoC Design and SoC Design for ES have a shared Canvas page. No compulsory books.

8 29 EXAMINATION Separate marks for different modules and integration project. Weighted average gives final mark, weights roughly reflecting time spent on each part. A module mark is computed from points per assignment. See Canvas site for detailed information; some details still to be provided. Attending all lab sessions is compulsory: Up to some degree, due to overlaps in course schedule, absence at lab sessions can be tolerated. Missed sessions will need to be compensated at other moments of the week; no assistance can be provided then.