Metode logičnega snovanja FPGA logična vezja in Xilinx Spartan-3E. Miha Moškon
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1 Metode logičnega snovanja FPGA logična vezja in Xilinx Spartan-3E Miha Moškon
2 FPGA logična vezja Večinoma so zasnovana na SRAM tehnologiji (ostala programabilna vezja uporabljajo EEPROM tehnologijo). Slabosti: ob izgubi napajanja se konfiguracija vezja izbriše, 1 SRAM predstavlja najmanj 5 tranzistorjev (prostor, energija). Prednosti: programiranje na terenu (Field Programmable), programiranje med izvajanjem (Evolware), konfiguracijo vezja lahko zapišemo v PROM.
3 FPGA logična vezja V grobem so sestavljena iz treh delov: konfigurabilnih logičnih blokov (CLB): sluţijo za implementacijo sekvenčnih ali kombinatoričnih vezij, vhodno/izhodnih blokov (IOB): programabilni do določene mere (smer, pomnjenje, električni nivo), programabilnih povezovalnih kanalov: različni tipi povezav, več različnih poti med dvema točkama, napovedovanje časovnih zakasnitev ni moţno, kompleksen routing.
4 FPGA vs. CPLD FPGA neobstojni (volatile) do nekaj milijonov vrat kompleksnejši routing Look-up Tables CPLD obstojni (non-volatile) do nekaj vrat predvidljive povezave programabilna polja
5 Spartan-3E XC3S500E CLB Vsak blok sestavljata 2 para rezin (slices), 1164 blokov je razvrščeno v CLB polje dimenzije 46x34. Vsako rezino sestavljata 2 4 vhodna LUT-a (Look Up Table), 2 pomnilna elementa, multiplekserji in carry logika (aritmetične funkcije). Rezine nastopajo v parih 2 tipa parov: levi pari: logične in pomnilne funkcije, sestavljajo jih SLICEM rezine (podpirajo implementacijo 16x1 RAM blokov ali 16-bitnih shift registrov z LUT-i), desni pari: logične funkcije, sestavljajo jih SLICEL rezine. Pari si delijo carry logiko.
6 Spartan-3E XC3S500E SLICEM
7 Spartan-3E XC3S500E SLICEL
8 Razporeditev rezin znotraj CLB
9 Look Up Table (LUT) LUT sluţi realizaciji logičnih funkcij. Bazira na RAM tehnologiji (vanjo vpišemo ţeljene vrednosti funkcije pri določeni kombinaciji vhodov). V FPGA vezjih je LUT glavni gradnik za realizacijo logičnih funkcij. Spartan-3E: 4 vhodi, 1 izhod (v MUX, aritmetično logiko, izhod iz CLB ali pomnilno enoto). Realizira lahko poljubno funkcijo 4-ih spremenljivk.
10 Multiplekser (MUX) Povezovanje z LUT-i nam omogoča realizacijo kompleksnejših logičnih funkcij. Dva tipa MUX-ov: F5MUX in FiMUX (i = 6,7 ali 8). F5MUX zdruţuje 2 LUT-a v rezini. FiMUX zdruţuje MUX-e iz iste ali druge rezine. FiMUX lahko realizira poljubno funkcijo z i-timi vhodi.
11 Povezovanje multiplekserjev
12 Spartan-3E XC3S500E IOB Programabilni vmesnik med pinom in FPGA logiko v notranjosti vezja. Pribliţno 25% od 232 IO blokov je samo vhodnih (input only). 3 glavne signalne poti: vhodna pot (moţnost zakasnitve in pomnjenja), izhodna pot (moţnost pomnjenja), three-state pot (moţnost pomnjenja, krmiljenje three-state driverja visoka impendanca).
13
14 Spartan-3E XC3S500E - ostali elementi CLB polje poleg CLB-jev vsebuje še: 20 2-portnih18kb blokov Block RAM pomnilnika (za shranjevanje večje količine podatkov), 20 Dedicated Multiplier 2 x 18 vhodnih mnoţilnikov (za mnoţenje, pomnjenje, barrel shift,...) Digital Clock Managers (DCM) (za nadzor nad frekvenco, faznim zamikom in eliminacijo zakasnitve ure clock skew).
15 Spartan-3E XC3S500E - routing 4 tipi povezav znotraj vezja: posebne linije za urin signal, 24 dolgih linij (majhna kapacitivnost, za visoko-frekvenčne signale), 8 skupin hex linij (za oddaljenost do 3 polj) 8 skupin dvojnih linij (za oddaljenost do 2 polj) direktne povezave (za oddaljenost 1 polja tudi diagonalno, ponavadi povezujejo polje z drugimi linijami). Preklopna matrika (Switch Matrix) zdruţuje vse tipe povezav preko celotnega vezja.
16 Spartan-3E XC3S500E - routing (2)
17 Spartan-3E Starter Kit Komponente: programabilno vezje Xilinx XC3S500E Spartan-3E FPGA, programabilno vezje Xilinx XC2C64A CoolRunner CPLD, 4Mb Platform Flash Configuration PROM, 64MB DDR SDRAM, 128Mb parallel NOR Flash, 16Mb SPI serial Flash. Osnovna ura je 50 MHz.
18 Spartan-3E Starter Kit (2) 2-vrstični LCD zaslon (2 x 16 znakov), PS/2 port, VGA port, 10/100 Ethernet PHY, 2 x RS-232 port, USB port, AD konverter, DA konverter, gumbi,...
19 Konfiguracija Vezje omogoča več načinov konfiguracije: direktno konfiguriranje Spartan-3E FPGA preko USB- JTAG logike (ob izpadu napetosti se konfiguracija izbriše), konfiguracijo shranimo v 4Mb Xilinx XCF04S Serial Platform Flash, konfiguracijo shranimo v 16Mb SPI Serial Flash, konfiguracijo shranimo v 128Mb parallel NOR Flash. Način konfiguriranja nastavljamo z Jumperji J30 (M0, M1, M2).
20 Delovno okolje Za programiranje uporabljamo Xilinx ISE WebPack paket (verzija 10.1), ki je na voljo na Xilinxovi domači strani. Ţe sprogramirane komponente v VHDL-u (npr. MicroBlaze Soft Processor Core).
21 Xilinx ISE WebPack Postopek izdelave projekta: File New Project Top-Level Source Type: HDL Device properties: Family: Spartan3E Device: XC3S500E Package: FG320 Speed: -4
22 Xilinx ISE WebPack Dodajanje VHDL datotek: Project New Source VHDL modul
23 Simuliranje Ročno generiranje testnih signalov (z vhd kodo): Project New Source VHDL Test Bench določanje poteka signalov v dveh procesih (en proces za urin signal, en proces za ostale signale) izpis poteka simulacije izberemo: Sources for: Behavioral simulation (levo zgoraj), kjer mora biti izbrana naša datoteka s testnimi signali, Processes (levo spodaj), Simulate Behavioral Model (levo na sredini).
24 Simuliranje Avtomatsko generiranje testnih signalov: Project New Source Test Bench WaveForm, nastavimo ţeljene vrednosti signalov, izpis poteka simulacije izberemo: Sources for: Behavioral simulation (levo zgoraj), kjer mora biti izbrana naša datoteka s testnimi signali, Processes (levo spodaj), Simulate Behavioral Model (levo na sredini).
25 UCF datoteka Pred programiranjem vezja moramo programatorju povedati, kareri pin na samem vezju naj se preslika v vhod/izhod, ki smo ga definirali v VHDL kodi. To naredimo v ucf datoteki (constraint file), ki jo dodamo v naš projekt. Datoteko urejamo tekstovno.
26 Xilinx ISE WebPack Sinteza in programiranje vezja: Sources for Synthesis/Implementation, Generate Programming File Configure Device (impact), Configure devices using Boundary-Scan (JTAG) auto, pri xc3s500e izberemo *.bit datoteko, v drugih dveh primerih damo Bypass, desni gumb na napravo xc3s500e Program OK.
27 Naloga Z logičnimi enačbami realizirajte 4-bitni števec, ki bo ob pritisnjenem gumbu štel navzgor, sicer pa navzdol. Ob pritisku na drug gumb naj se števec resetira. Števec naj vrednost poveča 1-krat na sekundo. Vsebino števca prikaţite na LED diodah na ploščici (LD0 do LD3).
28 Predlog rešitve Realizirajte vezje, ki bo vsako sekudno zgeneriralo pulz v dolţini 1 urine periode števec, ki postavi izhodni signal na 1, ko doseţe podano vrednost, sicer pa ga postavi na 0. Pri tem upoštevajte dejstvo, da je osnovna ura na ploščici 50 MHz. Pulz vključite v pogoj za spreminjanje vrednosti števca.
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