An OpenSource Digital Circuit Design Flow
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1 An OpenSource Digital Circuit Design Flow Davide Sabena Mauricio De Carvalho Free Software
2 Outline Introduction Problem Motivations Proposed Open Source method Digital Design Flow Commercial vendor part of the flow Open Source alternative solutions Commercial vs. Open Source tools Open Source Design: Real Cases Conclusions.
3 Introduction: Scenario Semiconductor devices are very complex components containing millions of transistors whose technology scales every year.
4 FROM TUBES TO INTEGRATED CIRCUITS
5 PENDRIVE 256 GB
6 SPEED OF COMPUTATION Pitagora 0.02 moltiplicazioni/sec Gauss 0.1 moltiplicazioni/sec Divisumma 1 moltiplicazione/sec PC moltiplicazioni/sec
7 THE PEARL 1 TERAFLOP
8 BIT TRANSMISSION 0.2 bit/sec 3 bit/sec bit/sec bit/sec bit/sec
9 THE PEARL OF TRANSMISSION 10 Tbps 1000 km 10 micron 2 c/m
10 MEN ANTS AND TRANSISTORS
11 MAGIC PAINT OF PROF. LAMBICCHI
12 Atomi, Bit, Soldi
13 MAGIC PAINT OF CARS
14 ANOTHER MAGIC PAINT
15 Introduction: Digital Flow The Digital Design Flow contains the exact procedures a design team must obey to correctly implement a hardware function in a Chip EDA Electronic Design automation T.niche Free trade zone
16 Introduction: Digital Flow The Digital Design Flow contains the exact procedures a design team must obey to correctly implement a hardware function in a Chip The increasing complexity of Chips and System-on-a-Chip (SoC) requires the insertion of many other tasks in the flow.
17 Introduction: Problem The correct development of a chip relies on many EDA/CAD tools used for different tasks in the Digital Flow but their licenses are very expensive and may exceed $200K/year There are three main commercial Vendors:
18 Introduction: Problem Each commercial vendor provide tools for performing all the flow but they are specialists at different parts of the design flow, obliging companies and developer to buy many licenses Mentor Graphics: is the best for Digital Functional Simulations Synopsys: is the best for Netlist Compiler, Power Analysis and Fault-Simulation Cadence: is the best for Analog Simulations and Physical Layout.
19 Introduction: Problem Small EDA/CAD vendors emerging on the market, most of the times, are bought by one of the 3 major companies From 1994 until today there were over 50 small companies acquired/merged to these 3 big companies EDA/CAD license costs reduce slowly due to the lack of strong concurrent companies and tools.
20 Introduction: Motivations Although there are several university programs reducing license prices, they continue to be expensive for poor universities New Application-Specific Integrated Circuit (ASIC) design ventures need a huge capital to start Also, there is a necessity to distribute these tools to poorer universities and start-ups.
21 The proposed Idea To provide a set of Open Source/Free EDA/CAD tools proper for ASIC design flow for small companies and university students To compare cost reduction and features among commercial and open source tools List success cases ASICs implemented on Chip using open source tools.
22 Main Open Source EDA/CAD Tools Fedora Electronic Lab (FEL) [1][2] Hand-picked set of free & open source tools and applications for high-end hardware design and simulation for VLSI design ( Alliance [3],[4],[5] Magic [6],[7],[8] Electric [9] Over 100 open source programs, scripts and libraries for Very Large System Integration (VLSI) design.
23 Alliance 12-year efforts spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris-VI, France) Complete set of free CAD tools and portable libraries for VLSI design. It includes: simulator logic synthesis tools automatic place and route tools A complete set of portable Complementary Metal-Oxide-Semiconductor (C-MOS) libraries is provided.
24 Magic Very-Large-Scale Integration (VLSI) layout tool originally written by John Ousterhout and his graduate students at UC Berkeley during the 1980s Features: Interactive layout editor corner stitching design-rule-checking Routing Simulation Stretching and compaction
25 Electric CAD system for custom IC layout (ASICs), schematic drawing, hardware description languages, and electro-mechanical hybrid layout Features: design rule checking simulation interface PLA generation compaction compensation routing VHDL compilation
26 Main Open Source EDA/CAD Tools Odin II [10][11][12][13] framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL available from the University of Toronto whereas the original Odin [11] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. odin-ii Verilog Synthesis tool generally targetting FPGAs
27 Main Open Source EDA/CAD Tools Odin II Odin II is an open source HDL elaboration environment that converts Verilog HDL designs and maps them to CAD flows targeting ASICs and FPGAs [11] Odin II is a significant improvement over its predecessor Odin, and this was achieved by including a parser and focusing on the design of the software tool, including the netlist data-structure[11]. odin-ii Verilog Synthesis tool generally targetting FPGAs
28 Commercial vs. Open Source vs. Electric odin-ii Verilog Synthesis tool generally targetting FPGAs
29 Commercial vs. Open Source Commercial tools: Vantages(+) / Disadvantages(-) Reliable Fast Working with state-of-the-art technology (<40nm) More User-friendly Maintenance/Support up-to-date License is very expensive (>$200K/year per license) Training is expensive Format compatibility issues to specific vendors.
30 Commercial vs. Open Source Open Source: Vantages(+) / Disadvantages(-) Free (GNU general public license) Growing number of developers There are FREE tutorials available Provides compatible formats Not working with state-of-the-art of digital circuits (130nm) Does not support big designs Many bugs to solve.
31 Open Source implemented ASIC LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France) developed several stable projects with Alliance:
32 Open Source implemented ASIC Magic VLSI project: Digi-Key page for the first MultiGiG chip that can be purchased through Digi-Key. The chip is sold under the Micrel name as part number SM802110, and is a MHz frequency synthesizer with LVPECL output, in a 24-pin QFN package.
33 Open Source implemented ASIC Odin II : Transistor estimates for 9x9, 18x18 and 36x36 multipliers, a case study
34 Conclusions VLSI design is an important course at electrical and computer engineering programs however, commercial VLSI CAD licenses are usually costly which many academic institutes and small companies may not be able to afford An alternative solution to VLSI CAD tools were presented Efficent Open Source tools to generate digital circuits Up to now, Open source tools are useful for small designs reaching at maximum 800K transistors.
35 References [1] Fedora electronic lab website. [Online]. Available at [2] Fedora SPINS website. [Online]. Available at [3] A. Greiner, and F. Petrot, Designing portable module generators using the Alliance CAD system, Southeastern Symposium on System Theory, pp ,March, [4] A. Greiner, L. Lucas, and F. Wajsburt, Designing a high complexity microprocessor using the Alliance CAD system, IEEE International ASIC Conference and Exhibit, pp , September, [5] Alliance website. [Online]. Available at [6] J.E. Varrientos, VLSI microprocessor design for classroom instruction, University/Government/Industry Microelectronics Symposium, pp. 0-75, June, [7] H.L. Martin, A CAD tool for circuit extraction from VLSI layout cells, Energy and Information Technologies in Southeast, pp , April, [8] Magic website. [Online]. Available at [9] Electric website. [Online]. Available at
36 References [10] K.B. Kent, F. Gharibian, and L. Shannon, Odin II An open source verilog HDL Synthesis Tool for CAD Research, IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp , May, [11] P. Jamieson and J. Rose, A Verilog RTL Synthesis Tool for Heteroge- neous FPGAs, in Field-Programmable Logic and Applications, pp , [12] Odin II website. [Online]. Available at [13] J.C. Libby, A framework for verifying functional correctness in Odin II, International conference on Field-Programmable Technology, pp. 1-6, December, 2011.
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