Chip Scale Package and Multichip Module Impact on Substrate Requirements for Portable Wireless Products

Transcription

1 Chip Scale Package and Multichip Module Impact on Substrate Requirements for Portable Wireless Products Tom Swirbel Motorola, Inc W. Sunrise Blvd. Plantation, Florida Phone: Fax: Abstract The challenge in developing portable wireless products is to continually reduce product volume, increase functionality, and decrease system cost. Historically, the industry has met the challenge through increased silicon integration and component miniaturization. However, with the introduction of multiband phones and the convergence of palm top computers and internet appliances with wireless devices, the technical approaches typically used to meet these challenges need to be addressed not only at the component level but at the system level. Being able to design these devices, with a small, light weight form factor, requires using highly integrated small outline components and a mother board substrate capable of effectively providing the required electrical interconnection. The choices made in component packaging and chip configuration, especially with respect to high I/O count integrated circuits such as digital signal processors, power management, memory, and microprocessors can significantly impact the technology required for the mother board and subsequently the cost. Component integration at the module level for circuit blocks, with a high degree of interconnectivity such as memory integrated circuits with baseband processor integrated circuits, has been shown to reduce the complexity of the motherboard required when compared to interconnection of single chip packages. In this study, a comparison of single chip packages in the baseband section of a cellular phone with a three-chip multichip MCM-L package and a two chip stacked die module identified the impact multichip packages have on motherboard complexity and size. In the case of the MCM-L approach, the motherboard construction went from a six layer microvia board to a six layer thru-hole board with a % area reduction in the baseband section and a % total area reduction. In the stacked chip design, a microvia motherboard was still required, but a baseband area reduction of 0% and a total motherboard size reduction of 5% was realized. Key words:. Background Chip Scale Packaging, Wireless Products, and Multichip Module Laminates. 0 Today, the portable wireless product marketplace is demanding products that are small, thin, low cost, and light weight with more functionality and better user interfaces. In addition, the convergence of portable wireless handsets with palm top computers and internet appliances is accelerating the need to be able to provide functional circuit elements which use the smallest and lowest cost technology possible. Advancements in IC integration, IC packaging, passive components, and PCB substrate technology are enabling the realization of the requirements needed for such convergent products. IC integration in devices

2 Chip Scale Package and Multichip Module Impact on Substrate Requirements for Portable Wireless Products such as the baseband processor is resulting in integrated circuits with I/O counts exceeding 96. IC packaging is enabling migration toward small outline packages using.75mm and.5mm u-bga technology. Implementing the evolutionary changes in component integration and packaging technologies, the industry has been able to keep pace with consumer needs. The component and packaging technologies that have enabled smaller, lighter products, has had a significant impact on the motherboard technology required for interconnection. As a result of smaller package sizes being combined with high I/O integrated circuits, the wiring capacity of the motherboard needed to be increased to effectively handle the increased routing density demand. In order to provide connectivity microvia high density interconnect, technology has been developed in the PCB industry,. Quantitatively, the impact at the mother board level is best shown by the trends in motherboard size and interconnect density. A graph of board size and component pad density over time is shown in Figure. The data provide a good snap shot of the overall industry trend with respect to board area and pad density for mobile phones. The data for current products (shown with an x ) is from combination of cellular products made by various manufacturers. It is important that while the pad density continues to increase, the board area has split into two distinct groups which may remain relatively constant. This is due to the realization of the products which these numbers represent can result from different physical designs and thus different component and substrates to enable them. For example, there is a two board approach that has a separate transceiver and key pad board, a single board approach which combines the transceiver and keypad on one board, and also an approach which uses one board with one- sided assembly. The approach chosen for a particular product enables a certain physical design but may require different component and mother board choices. This paper will discuss the choices available in IC packaging technology including single chip, stacked chip, and multichip BGAs, and CSPs, and the impact these technologies has on motherboard substrate requirements.. BGA Footprint Routing A major challenge in moving to progressively finer pitch I/O pads on a BGA package is the ability to route all the traces from the I/O pads on the mother board. As I/O count increases the ability to route traces on a fine pitch, package becomes even more difficult. The Clinton Chao model for square array packages is an effective tool for determining the effect on the motherboard I/ O number and pitch can have. The model provides a reasonable estimation of the design rules needed if conventional or microvia Printed Circuit Boards are used 4. In this section, the focus will be on devices in the 96 to 56 I/O range. The various design rules and board construction options that are needed to effectively route out a 56 I/O device at.8mmand.65mm are shown in Table. The actual routes for a 56 I/O device at.8mm and.65mm are shown in Figure. Table. Design rules needed to route a 56 I/O BGA at.8mm and.65mm pitch. Microvia + thru-hole Microvia (fine line) Microvia only #signal #signal layers layers - conv - microvia conv - microvia PCB type mmBGA -line / space 4.5 (mils).5 (mils) 4.5 (mils) -uvia / pad 5 / 0 5 / 0 5 / 0 -thru-via / pad 0 / 0 n / a n / a.65mmbga - line / space - uvia / pad - thru-via / pad. (mils) 5 / 0 8 / 7.8 (mils) 5 / 0 n / a. (mils) 5 / 0 n / a Pad density (pads/in ) x x x Year 9 6 Board area (in ) 0 00 top top metal innerlayer u-via thru-via Figure. Actual routing screen captures for a.8mm and Figure. Mobile phone board area and pad density data..65mm 56I/O BGA. Historical trends are from Prismarck Data, current data supplied by author. Both devices had the same connectivity in a logic circuit which used a -4- microvia motherboard. The motherboard had one

3 dedicated ground plane but not a dedicated power plane. The design rules were: 4 mil line / 5 mil space for all layers ( wire / track); 5 mil u-via / 0 mil pad; 0 mil thru via / 0 mil pad. The.8mm BGA used approximately 8 thru-vias and 65 microvias to route out while the.65mm BGA used approximately 75 microvias and no thru vias. The design rules chosen did enable a thru-via to be placed within the.65mm pad array. The number of vias used to provide connectivity deviated slightly from theoretical because of how the power and grounds were connected.. Cellular Transceiver Case Study A GSM cellular transceiver board was used to compare the single chip and multichip approaches. The motherboard and its subsection partitioning are shown in the figures in Figure. 4. Single Chip BGA Approach Currently, the most popular choice for IC packaging in portable wireless products is to use single chip ball grid arrays. The main ICs in the wireless product in this case study, the baseband processor, power management, memory, and RF/IF were all packaged in single chip Micro-Ball Grid Array packages. Ball Grid Array packages at.8mm pitch were used for the 00 I/O RF/IF IC, the 96 I/O baseband processor, and the 00 I/O power management processor. Ball Grid Array packages at.75mm pitch were used for the two 48 I/O memory devices. The interconnection required for connectivity is illustrated in the routing net diagram shown in Figure 4. Notice in Figure 4 that the densest routing is in the logic / baseband section with the most congestion occurring between the baseband processor and the memory. logic RF / IF logic RF / IF Figure. Transceiver board outline and major subsections. The two main subsections are the RF/IF and the baseband. The RF / IF is usually composed of discrete and modular components and an Application Specific Integrated Circuit (ASIIC). In this case study, the RF ASIIC had 00 I/O. The other major subsection is the baseband. The baseband section includes the digital signal processing, microprocessing, memory, and power management functions. Typically, it is the most silicon intensive section of a phone. In this case, the baseband section integrated circuits were comprised of the baseband processor which includes the microprocessor and digital signal processing functions at 96 I/O, the power management integrated circuit at 00 I/O, a static random access memory (SRAM) at 48 I/O, and a FLASH memory at 48 I/O. Three different designs were evaluated using the integrated circuit architecture described above. The first used single chip Micro-Ball Grid Array packages for each IC, the second a multichip package for the baseband processor and memory, and a third stacked chip memory. The three options were then evaluated with respect to motherboard complexity and board area. Figure 4. Net guides showing electrical connectivity. The design has a total routing density of ~0 in/in and a total pad density of 0 pads/in. In the logic section only, the routing density is ~55 in/in and the pad density is 540 pads/in. In order to provide optimum connectivity, microvia Printed Circuit Board technology was required. The Printed Circuit Board technology that was necessary to effectively provide connectivity had a four layer core with one microvia layer on each side (i.e. - 4-). The design rules needed included.004" lines / spades,.00" thru via with a.00" pad, and a.005" microvia with a.00" pad. The main need for the use of microvia board technology was to provide interconnection in the baseband section. 5. Multichip Approach An alternative transceiver design used a multichip package in the baseband section instead of single chip packages. The purpose of this design was to evaluate the impact the multichip package had on the mother board substrate technology needed for

4 Chip Scale Package and Multichip Module Impact on Substrate Requirements for Portable Wireless Products interconnection, board area, and interposer substrate technology. Other authors have previously presented products which were designed using this approach and discuss the electrical performance and cost tradeoffs 5,6. From a design standpoint, the two main reasons for evaluating the multichip approach would be to minimize some of the dense routing on the motherboard, thus enabling a simpler technology to be used and to try to reduce the overall component area compared to a single chip approach. Since the most dense routing is attributed to the interconnect between the baseband processor and memory, these were the ICs chosen for a multichip module. The topside layout of the module is shown in Figure 5. MCM Figure 5. Top side layout of baseband/memory multichip module. The module was a wirebond design and used a build-up microvia board as the substrate. The substrate was a doublesided core with filled buried vias and two build-up microvia layers on each side (i.e. --). The design rules for the module were.00" line and space,.008" drilled buried vias with a.08" pad, and.004" microvias with a.008" pad. These design rules enabled an overall area reduction of about 0% to 5% compared to three single chip. The single chip packages had a total I/O count of approximately 75 which the MCM package reduced to 40. The result was a Ball Grid Array pattern on the backside of the substrate which was able to be placed on a mm pitch. With the localized routing density between the baseband and the memory being constrained within the multichip module substrate, the pad and routing density of the motherboard are significantly decreased. The electrical connectivity guides for the motherboard using the module are shown in Figure 6. As a result of the reduction in pad and routing density, the motherboard needed was a conventional six layer thru-hole construction. The design rules were.005" line and space and.00" drilled via with a.00" pad. Figure 6. Connection guides for the six layer motherboard using a multichip module. The total pad density on the motherboard was reduced to 400 pads / in with the pad density in the logic area only being 460 pads / in. The routing density of the motherboard was 85 in / in with the baseband section having a density of 05 in/in. Compared to the single chip package approach, the baseband board area was reduced by % and the overall board reduction was %. 6. Stacked Chip Approach A hybrid of the single chip and multichip approaches which is beginning to gain momentum is the stacked or vertical chip package. Initially, the main application for the package is to stack FLASH and SRAM memory in a single BGA package. For a concise overview of the various packaging methods for this stacked chip packages, Reference 7 is recommended. A third design was achieved using stacked memory die in the baseband section of the phone. Referring back to Figure 4, it was anticipated that the stacked chip package would eliminate sufficient interconnect density to enable a simpler board construction and reduce board area. After finishing the design, no significant decrease in routing density occurred and a -4- microvia circuit board with design rules similar to the single chip approach were still required. However, a 0% reduction in the baseband area was achieved which resulted in a 5% reduction in overall board area. 7. Conclusion The increase in functionality requirements for portable products is driving the increase in IC I/O count and the reduction in component packaging size. In order to meet these requirements

5 IC packages are moving to successively finer pitch. The combination of these factors is causing an increase in the pad and routing density requirements for Printed Circuit Board substrates. This increase in routing and pad density is most evident in the baseband subsection of the device. When single chip, multichip, and stacked chip packaging alternatives are compared, the single chip, and stacked chip approaches place the greatest routing requirements on the motherboard with the multichip package the least. It is possible to design the multichip module such that enough connectivity is placed in the interposer substrate to enable a simpler PCB mother board technology to be used. The single chip packages used in this study also required the most mother board area and the stacked chip packages the least. However, it is possible that as single chip packages migrate to.65mm and.5mm, the difference in area reduction may not longer be realized. Going forward, the stacked chip approach probably offers the best near term alternative to single chip packages in selected applications. Longer term though, as additional functionality is added, the multichip or stacked multichip package approach should be considered. About the author Tom Swirbel is a Principal Staff Engineeer in the Advanced Product Technology Center at Motorola in Plantation, Florida. His major areas of focus are substrate and substrate design technologies. He has a B.S. Degree in Materials Science and Engineering from Wilkes University and a M.S. Degree in Solid State Science and Technology from Syracuse University. He holds 4 US Patents and Trade Secrets and has presented numerous papers at various IEEE, IPC, and IMAPS conferences. References. Tom Swirbel, Adolph Naujoks, and Mike Watkins, Electrical Design and Simulation of High Density Printed Circuit Boards, Proceedings of the 998 Electronic Components and Technology Conference, ECTC 98, Seattle, Washington, pp , June -4, Happy Holden, Advanced PWB s; Build-up Multilayers: Technologies and Design, Fabricating Advanced PWBs Using Build-up Technologies Workshop, San Jose, California, March 9, Ibid 4. Tom Swirbel, Substrate Requirements for Effective integration of CSP and MCM in Portable Wireless Products, International Journal of Microcircuits and Electronic Packaging, IJMEP, Vol., No., Third Quarter, pp. 48 5, Georg Meyer-Berg, A Digital Cellular Phone MCM A Manufacturing Report, Proceedings of the 999 International Conference on High Density Packaging and MCMs, Denver, Colorodo, pp , April 6-9, Fujitsu F0 Hyper Digital Cellular Phone. 7. Intel Corporation website 4