3-D Package Integration Enabling Technologies

Transcription

1 3-D Package Integration Enabling Technologies Nanium - Semi Networking Day David Clark - Choon Heung Lee - Ron Huemoeller June 27th, 2013 Enabling a Microelectronic World

2 Mobile Communications Driving Semi Growth Semiconductor Market Revenues ($ in billions) $140 $120 $100 $80 $60 $40 $20 Growth - $43B CAGR - 10% $ $ F Growth - $6B CAGR - 3% $36 $42 Growth - $6B CAGR - 2% $68 $74 Growth - $15B CAGR - 6% $47 $62 $ $292B 2017F - $380B Growth - $88B CAGR - 5% Growth - $7B CAGR - 5% $32 Growth - $11B CAGR - 4% $47 $58 $0 Mobile Phones & Tablets Consumer Computing Networking Automotive Other* Source: Prismark Partners. February 2013 * Other includes Medical, Industrial, Military and Aerospace 1

3 Three Mobile Market Segments High End/ Premium Footprints Get Larger & I/Os Increase TMV PoP: Top 0.4mm pitch and Bottom I/O > 1000 Thin bare die PoP, bare die FC M BGA and bare die POSSUM Thermal considerations will impact structural choice Low power wide I/O die stack interface Mid Range Less Aggressive Although Thin with Substantial I/O TMV PoP for 12mm-15mm [8mm-17mm currently available] Solder ball pitch less aggressive at 0.5mm to 0.4mm WLCSP footprint increasing Memory ~300 I/O expected to due to future needs Basic/ Utility Lower cost / adequate performance tradeoff zone Hybrid platform Solder ball pitch at 0.4mm allows for individual attach onto PWB WLCSP footprint increasing, same concerns as above Memory I/O less demanding 2

4 Thin Is In! 3

5 Advanced Package Integration Board Level Smaller Form Factor Larger Wafer Level Die Die Level Interconnect Density & Functionality 4

6 Advanced Platform Embedded Die Packaging Substrate Level Passive Components Active Die Wafer Level Die Single Die Multi-Die 3D Package Single Die Multi-Die 3D Pkg Passive integration Internal EMI shielding possibilities Multi-die capability more than one die may be embedded Two-sided construction top side components may be mounted 5

7 Embedded Die in Panel Economy of Scale! 200mm Phase 1 300mm Phase 2 300mm 300mm 3D Phase 3 Panel 3D Panel Process Development Phase 4 6

8 Apps Processor w/memory (using PoP TMV ) Thin is in! Embedded die solutions prevailing Smaller form factor Total package profile < 1.0mm required Higher electrical performance Embedded Passive Substrate Embedded passive components WLFO on bottom POSSUM Increasing number of apps processors with embedded caps in the substrate 7

9 3D Wafer Level Fan-out Structures Key enabling technologies for extensions into 3D Thru mold via (TMV ) Fine pitch copper pillar CoC possum 3D PoP TMV 3D Die on Pkg Die Die Die 3D F2F 3D Stacking Die Die Standard WLFO structure 8

10 3D CSP TSV Vertical Stacks, cont. Application Processor, cont. Wide I/O-2 memory die now required ~1800ubumps ; > 25.6 Gbps 20-28nm (Cu pillar = 6-10um dia. TSV) Substrate & die = ~16x16 & ~12x12mm respectively ~1200 BGA product Heat spreader attach: necessary 9

11 Interposer Platform Development Five primary interposer solutions 2.5D-SOS: silicon on organic substrate Silicon Memory ASIC Organic Substrate D-GOS: glass on organic substrate Glass Memory ASIC Organic Substrate D-ADO: adv. dual organic substrate Memory Organic Substrate -1 ASIC Organic Substrate -2 Memory ASIC 2.3D-AHO: adv. hybrid organic substrate Organic Substrate D-DOS: dual organic substrate Organic OS-1 Memory Organic Subst -2 10

12 General Comparison Between TMV WLFO & TMV PoP TMV WLFO TMV PoP Now 2015 Projection WLFO PoP (MR) WLFO PoP (MR) PoP (TC) Overall Package Thickness 0.640mm 0.540mm 0.350mm 0.320mm 0.260mm MIF Pitch 0.4mm 0.4mm 0.3mm 0.3mm 0.3mm L/S Capability 12/12 18/18 8/8 15/15 15/15 Metal Layer Count 1L 6L 2L 4L-C 4L-C Metal Layer Count Capability 2L (in dev) N/A 3L N/A N/A Package RT Warpage ~80um (1L) ~120um (6L) ~300um (2L)* ~300um (4L-C)* ~300um (4L-C)* Package HT Warpage ~20um (1L) ~60um (6L) ~125um (2L)* ~200um (4L-C)* ~200um (4L-C)* Normalized Cost 1.5 ~ Approaching Parity *Note: Based on simulation with current materials. Actual results are expected to be better with material improvements. 11

13 Detailed Stack-up Comparison - back to Thin is In A6 A6 A7 A5 A3 A2 A4 A3 A7 A5 A3 A2 A4 A3 A3 A1 A1 TMV WLFO TMV PoP Now 2015 Projection TMV WLFO TMV PoP (MR) TMV WLFO TMV PoP (MR) TMV PoP (TC) ITEM UNITS NOM NOM NOM NOM NOM A3 Mold Cap mm A2 Substrate / RDL mm A1 BGA Stand-Off mm BOT PKG Thickness mm Note: Values listed reflect nominal values, and do not take into consideration coplanarity or package warpage. 12

14 Summary Tremendous growth in mobile markets fueled by consumer demand for increased mobility, functionality & ease of use Drives increase in functional convergence to 3D integration of IC devices providing complex & sophisticated packaging solutions Packaging solutions for mobile application Embedded passives in substrate a proven package technology Embedded die in wafer Provides a robust platform for extensions into more advanced three dimensional structures addressing both profile and performance 3D PoP WLFO : provides dramatic reduction in z-height and opportunity for improved electrical performance F2F WLFO : provides most optimum low-latency electrical interconnect for mobile computing and networking applications TSV for mobile products Extreme bandwidth & high end performance 13

15 Thank You Enabling a Microelectronic World