3D technology evolution to smart interposer and high density 3D ICs

Transcription

1 3D technology evolution to smart interposer and high density 3D ICs Patrick Leduc, Jean Charbonnier, Nicolas Sillon, Séverine Chéramy, Yann Lamy, Gilles Simon CEA-Leti, Minatec Campus

2 Why 3D integration? To integrate complex electronic systems on silicon 3D ICs System on board (Smatphone PCB) A silicon interposer With very heterogeneous dice on it (various substrates, various technologies co-existing, various chip makers ). Smaller, more functionality, higher performance 2

3 Facts & Figures CEA-Leti: an early-adopter of 3D, thanks to its background in MEMS & Microelectronics (first TSV patent in 1988) R. Cuchet et al, 1988 Laser drilled TSV Today, 100+ people full time on 3D integration Present to major IC conferences (regular presence at IEDM) and packaging conferences. An average of 30 papers / year 15 3D patents in 2011 Letiat the heart of Grenobleecosystem on 3D 3

4 Contents Si interposer 3D IC Towards smart interposer Towards high density Conclusions 4

5 Silicon Interposer Technology Interposer size: 26x26mm² (warp management required) TSV: 10x100µm Cu damascene routing : Metal1-Via1-Metal2, 0.5µm line/0.5µm space Micro copper pillars: Pitch 50µm, /interposer TSV exposure RDL and passivation: 10µm Line / Space, one level Large copper pillar: pitch 500µm, height 70µm Micro Cu pillar Damascene TSV TSV exposure RDL and Passivation Large Cu Pillar Joined Lab J. Charbonnier et al., ESTC

6 TSV and Front side routing SEM Cross section after front side passivation opening Copper in TSV stabilized for further integration process Dense routing 0.5/0.5µm design performed successfully Line 2 Line 1 Via L/S=0.5/0.5µm L/S=0.7/0.7µm TSV 10x100µm L/S=1/1µm J. Charbonnier et al., ESTC 2012 Joined Lab 6

7 Front side Copper micro pillar 10µm height, Ø25µm and 50µm pitch Deposit uniformity within wafer: +/- 1µm Cu/Ni/Au stack for oxidation protection per interposer Au capping Ni diffusion barrier Cu base Joined Lab J. Charbonnier et al., ESTC

8 Backside RDL and Bumps Zoom top view on RDL and pillars RDL L/S=10µm Organic passivation by spin coating Large bumps Ø250µm and 500µm pitch pillars Cu/Ni/Au electroplating Stripping, seed layer wet etch Total thickness 70µm Passivation RDL SEM tilted 60 bump J. Charbonnier et al., ESTC

9 Interposer cross section Good integrity of the overall structure: no delamination No copper extrusion or residue between TSV and Line 1 No copper extrusion or residue between TSV and Backside RDL J. Charbonnier et al., ESTC

10 Si interposer on tape (200mm wafer) 100µm thick interposer on dicing tape after debonding J. Charbonnier et al., ESTC

11 Electricaltests Chain A Chain B Chain C cumulative 100% yieldon 100 and 1000 TSV chains J. Charbonnier et al., ESTC

12 Si Interposer Demonstrator Features Cu TSV, AR10 2 to 4 layers routing, Damascene thick copper, L/W 0.5/0.5 x 1.4μm Temporary bonding Thinning, Stress Monitoring, Warp Management Chip Chip A Chip B Cu Pillar Under -fill Si-IP Organic substrate TSV Si-IP Ken Miyairi, Masahiro Sunohara, Jean Charbonnier et al, IMAPS, San Diego 09/

13 Interposer evolution High Density Interposer More wires Smart Interposer More than wires 13

14 Smart interposer: More thanwires Thermal Interposer Computing Power Lighting Application processor Active Interposer Power management High Voltage External I/O (Mature node) Passives Interposer Smart interposer Photonic Interposer RF Platform for Baseband Lighting Application Processor (decoupling capacitance) Health: Implantable electronics Servers Data centers Computing 14

15 Smart interposer for a pacemaker 3D Si capacitors integration in implantable module ~1.2mm RF Die PICS ~900um SiP Package for pacemaker: RF Transceiver SAW Filter 400MHz & 2.4GHz Matching network with integrated coils Decoupling capacitances 14mm 11.2mm 8mm - 40 % area decrease - 25 % height decrease 6.45mm Si interposer Collaboration between: Integrated passives in Si interposer leads to 40% size reduction of the RF module compared to PCB Source: Vivarès, Voiron, Lamy, et al. LETI IPDIA-SORIN -Minapad

16 Contents Si interposer 3D IC Towards smart interposer Towards high density Conclusions 16

17 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip) 17

18 Wide I/O Demonstrator Wide I/O SDRAM JEDEC memory standard released Jan TSV s Ø 10 μm, AR 8, Pitch 40 μm, Number1016 Compatible with FD-SOI Chip to Chip Cu Pillars Ø20 μm, Height20 μm, Pitch 40 μm, Number1016 SoCto SubstrateCu Pillars Ø55 μm, Height 40 μm, Pitch >200 μm, Number933 FBGA Package Size 12x12mm, Ball Pitch 0.4mm,Ball Matrix 29x29, 1.2 mm thickness Si - Wide I/O Memory TSV 80µm Cu Pillar Si - SoC WIOMING, G.Kimmich, G.Qualizza

19 3D Partitioning : Digital - Analog Top - Digital Bottom - Analog BGA BEOL Die - BGA connection Die - die connection TSV Wireless application High definition video transmitter, >1GHz Integration technology proven and concept demonstrated TSV + 7 metal layers, 65nm technology Cost evaluation dependant on product complexity and design Cu TSV Cu TSV Cu RDL 3D Integration of a Wireless product with Design Partitioning G. Druais et al., 3DIC

20 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip) 20

21 Logic-on-logic : 3D Asynchronous NoC Easily stackable logic tiles A set of tiles will give you the performance for your application Increase number of applications for a single die, reach required volume production Constraints? High bandwidth between dies, Easy staking, no clock distribution issues Power distribution, Testability, Fault Tolerance Proposal : 3D Asynchronous NoC Fast serial link Full asynchronous logic Demonstration in 2014 NoC Serial Links 2D NoC Router 3D NoC Router Processing Unit 21

22 Active Interposer Concept Heterogeneous integration rationale: Small dies shorten new process introduction and improve overall yield Analog design and IOs doesn t shrink a lot with process technology Short interconnect improves signal and power integrity SoCpartitioning into several dies, with different technology nodes Processing layer: High performance multicore processors Multi-core SoC SDRAM Memory layer: High bandwidth, Wide data interface Active Interposer: Analog, interconnect, memory control and I/O peripherals Multi-core SoC Multi-core SoC Demonstration in

23 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip) 3D Cache memory on manycore processor Fine grain 3D partitionning ( 10µm pitch) 23

24 3D Cache Memory on manycore Non-uniform Memory Architecture (NUMA) : splitinguniform cache into multiple banks interconnected with a NOC 3D stacking adding flexibility, high capacity and a gain on power consumption High bandwidth and fault tolerance 1Oµm TSV pitch required >10000 TSVs per chip Eric Guthmulleret al., Adaptive Stackable 3D Cache Architecture for Manycores, ISVLSI2012

25 TSV shrinkfor costreduction Surface Cost TSV surface + Keepawayzone (KAZ) Active + M1-Mx layers Numberof TSVs(today1000 for Wide IO memory) Si KAZ TSV diameter 6 Surface occupied by x TSV [mm²] Surface [mm²] TS V Si TSV diameter [µm] 25

26 LowdiameterTSV 15µm 15µm 3µm M1 Reducing Si thickness: 15µm High Density TSV s demosntrated in 65nm MOSFETS M5 Investigation on TSV impact on 65nm CMOS devices and circuits H. Chaabouni, M. Rousseau, P. Leduc et al., IEDM

27 Cu direct bonding Full characterization of Cu/Cu direct bonding for 3D integration, Rachid Taibi, Léa Di Ciocciob et al., ECTC2010 >90% yield of daisy Chain with x3µm² Cu contacts Contact resistance: 2,5 mω Contact chain SEM cross section Optical top view Acoustic image of bonding 0.5 µm thick line standard deviation σ ~ 1.2% Resistance (Ω) 27

28 Conclusions Si interposer has been successfully demonstrated in Leti Smart Interposers Promising solution to integrate more devices on Si 3D ICtechnology is ready for coarse grain partitioning ( 500 TSV/mm²) Promising solution to reduce the cost of advanced SOC (<28nm) Fine grain partitioning for higher performances Increased density of TSV and interconnects Low TSV diameter required 28

29 Thanks for your attention