Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology

Transcription

1 Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology JinYoung Khim #, Curtis Zwenger *, YoonJoo Khim #, SeWoong Cha #, SeungJae Lee #, JinHan Kim # # Amkor Technology Korea 280-8, 2-ga, Sungsu-dong, Sundong-gu, Seoul , Korea JinYoung.Khim@amkor.co.kr * Amkor Technology Inc 1900 South Price Road, Chandler, AZ 85286, USA Curtis.Zwenger@amkor.com corresponding and presenting author I. SUMMARY During the past few years, Wafer Level Fan-Out (WLFO) has emerged as one of the leading advanced packaging technologies for the electronics industry, providing the opportunity for increased I/O density, reduced package footprint, improved electrical/mechanical performance, and reduced cost. WLFO is now well-established as a viable alternative to conventional laminate-based and wafer-based packages. More recently, WLFO has shown its ability to extend itself into more innovative and advanced structures to support the increased functionality and performance requirements of next generation mobile and networking devices. By applying enabling technologies, such as Thru- Mold Via (TMV ) Fine Pitch Copper Pillar (FP CuP) bumping, and Chip-on-Chip (CoC) bonding, WLFO extends its applications and benefits to the area of 3D Packaging. Two such structures are 3D PoP (Package-on-Package) WLFO and Face-to-Face (F2F) WLFO. Positive development and qualification results indicate that WLFO has the ability to extend itself beyond simple 2D structures to meet the needs of more advanced applications and device technologies. II. INTRODUCTION The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on-Chip, and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature characteristics associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper reviews the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs are compared to current competing packaging technologies. Process & material characterization, design evaluation, and reliability data are presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products. III. 2D WAFER LEVEL FAN-OUT Two-Dimensional (2D) WLFO is well documented as a robust and reliable wafer-level package (WLP) technology for electronic devices. Figure 1 illustrates a cross section of a typical 2D WLFO structure. Fig 1. 2D WLFO structure The fundamental WLFO technology is based on the embedding of die into a molded wafer (also referred to as wafer reconstitution ). The molded wafer is then processed through standard wafer-level packaging processes to create the final package structure. The active surface of the die is coplanar with the mold compound, allowing for the fan-out of conductive copper traces and solder ball pads into the molded area using conventional redistribution layer (RDL) processing. A cross section photo of the die and mold transition area is shown in Figure 2. Fig 2. SEM of WLFO cross section

2 The elimination of a conventional laminate substrate and utilization of wafer-level packaging s superior design and feature size capabilities provide many benefits of WLFO, including: Increased I/O density Reduced form factor (including z-height) Improved electrical and mechanical performance Multi-chip capability Outstanding cost/performance capability (through co-design optimization) Scalability within a heterogeneous assembly platform Opportunity for advanced 3D structures Although WLFO is technically a wafer-level package, it retains one of the key characteristics of a conventional molded laminate package the mold compound itself. An example of a WLFO package is shown in Figure 3. The intrinsic benefit of the mold compound is that it has shown to improve board level reliability (compared to an equivalent size WLP structure) due to the reduced CTE mismatch between the mold compound and motherboard. Another key attribute of the molded area is that it provides a media to create innovative 3D structures. Fig 3. 2D WLFO package Fig 5. 3D WLFO key process steps Although the 3D PoP WLFO structure looks very similar to a conventional laminate-based TMV PoP (as shown in Figure 6), 3D PoP WLFO has additional technical merits due to the use of wafer level packaging technology. For example, the WLP process uses much thinner conductive and dielectric layers compared to typical laminate substrate build-up technology. The resulting WLFO RDL stack-up provides improved electrical performance due to less parasitic elements. In addition, the elimination of additional interconnection features, such as wire bonds or flip chip bumps, provides the opportunity for cost reduction. And finally, the ability to thin WLFO packages while still in wafer form allows the capability to create very thin package structures for PoP applications. (a) (b) Fig 6. Comparison of package structure (a) WLFO type (b) PCB type These advantages of 3D PoP WLFO enable unique applications for mobile devices, such as the multi-stack structure shown in Figure 7. By controlling individual package thickness to less than 300um (as shown in Table 1), a final 4-package stacked thickness of 1.2mm can be achieved. IV. 3D WAFER LEVEL FAN-OUT Standard wafer level fan-out technology can be expanded in the vertical (z) direction when connecting it as a 3D PoP structure, as shown Figure 4. This is enabled through the use of advanced laser and via fill processes. Fig 4. 3D WLFO PoP Package structure The front side (i.e., active die side) RDL process for 3D PoP WLFO is nearly the same with that of standard 2D WLFO. However, a laser drilling (or equivalent) process is used to expose an RDL feature from the back side (i.e., the mold side). Figure 5 illustrates the key process steps for the 3D PoP WLFO fabrication process. Fig 7. Example of 3D PoP WLFO memory stack TABLE I PACKAGE DIMENSION (SINGLE PoP) Unit: mm Item WLFO Mold cap 0.15 Substrate (WLFO: 2 layer RDL) 0.05 BGA (0.4mm pitch) 0.10 Total thickness (max) 0.30 Another attribute of 3D WLFO is that, through the use of TMV technology, the active die side can be oriented faceup and exposed to the environment an ideal condition for biometric sensing applications. Fine pitch vias are used to

3 make connections between the front (die) side and back (mold) side, to translate the solder ball pads to the back side of the package. This structure is illustrated in Figure 8. EMC Die D1 CuD2 D3 Fig 8. Sensing application for 3D WLFO The core technology of WLFO 3D PoP is the TMV process that drills vias through epoxy mold compound (EMC) using laser ablation. The vias are then filled with a conductive material to establish a reliable electrical connection with the underlying RDL feature. One of the constraints of the TMV structure is its limitation in creating increasing finer pitch and deeper via geometries. Process characterization is required to ensure the via structure can endure the thermal and mechanical stresses of the TMV process. The intense localized heating during the laser drilling process, coupled with a high plasma gas environment, can cause oxidation and contamination on the targeted copper RDL pad on the front side of the package. Process optimization is critical to ensure a robust TMV process and a contamination-free and oxide-free electrical interface. In addition, EMC materials are highly concentrated with silica filler. When subjected to laser ablation, the filler breaks into very fine particles that can contaminate the surface of the wafer. To minimize the risk of contamination, special cleaning methods are applied after the laser ablation process. Figure 9 illustrates the laser drilling process and shows examples of drilled and filled vias. K The top package in a TMV PoP stack typically establishes its connection by nesting its solder balls directly on top of the underlying package s TMV structure (as previously illustrated in Figure 7). In cases where redistribution of the TMV pattern is needed on the mold side of the package, direct laser patterning techniques can be selectively applied, either on a polymer layer or directly on the EMC surface. Figure 10 shows redistribution patterns connecting the TMV structures to the BGA pads by using direct laser ablation on either the EMC surface or on a polymer layer. Fig 10. Redistribution layers and TMV structure on EMC (left) and on a polymer layer (right) V. FACE-TO- FACE WLFO Another innovative 3D structure is Face-to-Face WLFO. This fan-out package, shown in Figure 11, has a depopulated BGA pattern within which a second die is connected directly to the underlying WLFO RDL structure. This direct chip attach methodology results in a small form factor package that provides very low latency signal path for high speed data transfer between memory and logic components. Fig 11. F2F WLFO Structure The general process flow for F2F WLFO is illustrated in Figure 12 below. Laser Drilled via Fig 12. Overall process of F2F WLFO After via filling Fig 9. Thru-Mold Via (TMV ) process The core technology (and key challenge) for F2F WLFO processing is pattern alignment. A molded wafer (as opposed to a standard silicon wafer) shrinks and expands due to the thermal stress it experiences during WLFO processing. In addition, the actual die stepping distance of a molded wafer has a more significant deviation from the design value due to the die attach machine s placement tolerance. Consequently, design, material, and process optimization is needed to provide the most robust die to die bonding results. For example, the die attach machine s placement tolerance must

4 be accounted for in the F2F design rules. Also, optimized mold compound formulations, with a low coefficient of thermal expansion (CTE) and low moisture absorption, can also provide more consistent process results. And finally, a molding process that distributes uniform temperature and pressure should be used to minimize the die shift during molding. Figure 13 shows the dramatic impact of the chip attach and molding processes on the dies location within the WLFO wafer. Fig 14. F2F molded wafer with RDL Fig 15. F2F interconnect area on the molded die (1200 total I/O) Fig 16. Fine pitch (40um) copper pillar F2F interconnect pattern VI. QUALIFICATION AND RELIABILITY LEVEL OF 3D WLFO Reliability tests have been performed on 3D PoP and 3D F2F WLFO packages. The status and results of these tests are shown in Table II below. Fig 13. Die position tolerance after chip attach and molding During the redistribution processing of a F2F WLFO structure, optimized conditions must be established that control the distortion and warpage of the molded wafer within allowable tolerances. This is a key element to ensure the successful alignment of the CoC interconnection during the chip mounting process. Figure 14 shows a F2F test vehicle s molded wafer with RDL patterning applied. Note the two gray rectangular shaped patterns within each package body that define the F2F interconnect area. Figure 15 shows the actual F2F interconnect area on the molded die. Figure 16 is a picture of the molded die s fine pitch interconnect pattern. This F2F WLFO test vehicle s overall package size is 14x14mm, the molded die and CoC die are both 8x8mm, and the final F2F package thickness is 250um. The number of interconnects on the CoC die is 1,200 with a pitch is 40um. TABLE II 3D PoP and 3D F2F WLFO Reliability Test Results 3D PoP 3D F2F MSL L3 260 C Temp Cycle Condition B 500 cycles 1000 cycles Ongoing uhast 85 C/85% RH High Temp 150 C Storage 1000 hours Board Level Temp Cycle & Reliability Drop Shock Ongoing Ongoing VII. CONCLUSION Conventional two dimensional WLFO packaging provides a robust platform for extensions into more advanced three dimensional structures. Two innovative 3D WLFO packages, 3D PoP and F2F WLFO, have been successfully

5 created through the use of key enabling technologies, such as TMV, FP CuP bumping, and CoC bonding. The resulting 3D PoP WLFO package experiences a dramatic reduction in z-height and the opportunity for improved electrical performance both critical attributes for the demanding mobile device market. The F2F WLFO package provides the most optimum low-latency electrical interconnect for mobile computing and networking applications. Through the development of accurate design rules and the optimization of key assembly processes, a robust 3D WLFO platform has been established. Reliability test results are positive. New, innovative WLFO packages, such as 3D PoP and F2F WLFO, are poised to play a key role in supporting the demanding packaging requirements for mobile and networking applications. ACKNOWLEDGMENT The authors would like to thank the members of the Amkor Korea R&D team, including SungKyu Kim, JuHoon Yoon, Glenn Rinne, and Choon Heung Lee, and the Advanced Package Development team in Research Triangle Park, NC, including Dean Zehnder, Riki Whiting, and Junghee Ko, for their role in the development of the 3D WLFO package technology.