James Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003

Transcription

1 Challenges for SoC Design in Very Deep Submicron Technologies James Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd,

2 Contents Introduction and Outline VDSM technologies The challenges to Design Technologies Opportunities for Design Innovations System Level Chip Level Summary 2

3 Introduction As process technology continues to advance at the rate of ~0.7/3yrs (Moore s law), the number of available transistors is outgrowing the ability to use them The inability of efficiently designing with advanced process technologies is slowing-down the adoption of new process technologies and potentially stalling new technology development To solve this problem, new innovative design technologies (DT s) are required at every level of design 3

4 Outline Major design challenges for VDSM technologies Design productivity Power consumption Manufacturability Opportunities for DT innovations Chip-design point-of-view System-level co-design 4

5 Design Challenges with VDSM technologies 5

6 VDSM Technologies Technology Vdd (Volts) Core gate oxide (A) No. of Metal layers Dielectric constant Metal pitch - M1(um) Metal pitch - Others (um) Resistivity - M1 (ohm-cm) Resistivity - N+/Poly (Ohm/Ct) Resistivity - via (Ohm/Ct) Ca (af/um) Cf (af/um) Cc (af/um) NMOS Vt (Volts) PMOS Vt (Volts) NMOS Idsat (ua/um) PMOS Idsat(uA/um) NMOS Ioff (PA/um) PMOS Ioff (PA/um) kgates/mm^ Gate Delay (ps)

7 Design Productivity - The 1 st VDSM Challenge Design complexity usually causes poor design productivity and high design cost Transistor counts and speed increase exponentially Demand for increasing functionality, low cost & TTM More analog circuits & memories are being embedded Previously ignorable effects (e.g. noise, cross-talk, substrate noise, interconnect parasitic-rc) are becoming the critical issues kgates/mm^ Technology 0.13u CMOS 7430 x M X tor 7

8 Interconnect-Parasitic RC In VDSM, gate delay is much less than interconnect delay Total interconnect length can reach several meters Interconnect delay can be as much as 90% of total path delay in VDSM circuits The parasitics from interconnect become a dominate factor which often causes timing issue in chip design Technology Vdd (Volts) No. of Metal layers Dielectric constant Resistivity - M1 (ohm-cm) Resistivity - N+/Poly (Ohm/Ct) Resistivity - via (Ohm/Ct) Ca (af/um) Cf (af/um) Cc (af/um) Gate Delay (ps)

9 Power Consumption - The 2 nd VSDM Challenge Power has become a big issue in nanometer technologies Increasing transistor counts, chip speed, and greater device leakage are increasing both dynamic & static power consumption (P C*Vdd 2 * F + Ioff) Beyond 90nm technology, it is estimated that static power could be higher than active power Leakage/Active Contribution to Total Power Ioff (pa/um ) NMOS PMOS Vdd Technology Vdd (Volts) Power (Watts) Leakage Active Power 0.25um 0.18um 0.13um 0.10um 0.07um Technology Source: EETimes June 17,

10 Manufacturability - The 3 rd VSDM Challenge Continuous scaling of process technology has created problems in yield and reliability and testability Variability in process makes design more unpredictable Fab s are adding more design rules to address the issues, requiring more innovative DT s to implement them Gate Oxide (A) Technology M1 Pitch (um) Gate oxide (A) M 1 P itch (um ) 10

11 Evolution of Manufacturing Specs (or requirements) 0.8u 0.65u 0.5u 0.35u 0.25u 0.18u 0.13u 0.09u VDD x tor/cm^2 LDR/EDR PKG DR 5.0v 3.3v 2.5v 1.8v 1.2v 1.0v <1M More & more rules are being added to manufacturing spec. while x tor count increases and design margin decreases 2M 5M Antenna Dummy Fill OPC/SRAM bit cell Preferred LDR EM/IR Drop Parasitics (RC) Noise/X-talk 20M 50M 130M Dual Via s Parasitics (RCL) Leakage/Power More. 11

12 Manufacturability (cont.) -The 3 rd VSDM challenge As more functions are being integrated, the needs for Design For Test (DFT) is increasing: Improve Test Coverage Reduce Test Time Reduce Tester Requirements Ease Silicon debug & FA effort Self-repair Test costs in VDSM SoC designs Cost is reaching 60% of the total product cost 12

13 Major Design Challenges -The Summary Design Productivity More transistors are available for higher degree of on-chip integration with second-order effects becoming critical Power Consumption Increases due to more integrated transistors, higher speeds, and greater device leakage Manufacturability Yield Reliability Testability 13

14 Opportunities in Design Technology 14

15 Design Technology for SoC Design Technology includes: Design Libraries (IP s) Design TFMs (Tools, Flows and Methodologies) SoC design can be roughly divided into 4 major areas (design levels): System, Logic, Circuit, Physical There are many design tasks in each design area. In general, 3 TFMs are associated with each design task: Construction Analysis Correction 15

16 Design Technology for SoC Design Areas Design Tasks Design TFM s System Design Logic Design Placement & Route Construction Circuit Design Layout Design Rule Check Analysis Physical Design Func./timing Simulations N Pass? Correction Y Manufacturing Mask making 16

17 Design Technology for SoC Each design level used to operate separately or with minimum interaction from each other. But in recent years, due to the need to increase design productivity, the coupling between the design levels has been greatly enhanced In general, there are two major directions being pursued in enhancing the design capability: TFM Development: correct-by-construction Construction Analysis Correction Construction Analysis Design starts at a much higher level of abstraction 17

18 Product Development Evolution Design higher level Specifications System Design HW/SW Co-sim IC Components System Design 1980s Chipset Design Complexity System Design HW Design Productivity SW/Drivers 1990s SoC & Firmware System Integration HW 2000s Software Drivers 18

19 System Level Design System level co-design methodology has become an economic necessity for SoC design due to increasing complexity of the designs is the most effective way today to address productivity issues in SOC design Although TFM s for system level design have been advancing at a great pace recently, there is more that needs to be done to keep up with the advancements in process technology For VDSM SoC designs, we believe that a Platform Based design methodology will be the next design paradigm 19

20 Platform Based System Level Co-Design Methodology Platform based design is dominated by Memories & processors Combination of memories & processors allows more firmware on-chip which can then be used to: Produce design derivatives Enable redundancy or make functional corrections due to process defects or variability Improve performance without silicon re-spin All the major blocks are pre-verified with the silicon so that all the secondary effects (interconnects, x-talk, noise etc.) from VDSM are addressed ahead of time 20

21 Platform Based Design System architecture Hardware Synthesis SW-HW Co-SIM Software Development Silicon Implementation ROM DSP SRAM ROM DSP SRAM ROM IP s Chip-1 Audio SRAM SRAM SRAM Video Analog IP s RISC ef ROM Chip-2 Chip-3 21

22 Opportunities for System Level Design for VDSM SoC System architecture Hardware Synthesis SW-HW Co-SIM Software Development Silicon Implementation ROM DSP SRAM ROM DSP SRAM ROM IP s Chip-1 Audio SRAM SRAM SRAM Video Analog IP s RISC ef ROM Chip-2 Chip-3 22

23 Opportunities for System Level Design for VDSM SoC System architect design environment for Platformbased designs High level design partitioning and hierarchy Optimization between chip density, performance, power, manufacturability and design time Fast functional simulation (hw/sw co-simulation) 23

24 Opportunities for System Level Design for VDSM SoC System architecture Hardware Synthesis SW-HW Co-SIM Software Development Silicon Implementation ROM DSP SRAM ROM DSP SRAM ROM IP s Chip-1 Audio SRAM SRAM SRAM Video Analog IP s RISC ef ROM Chip-2 Chip-3 24

25 Opportunities for System Level Design for VDSM SoC System architect design environment for Platformbased designs High level design partitioning and hierarchy Optimization between chip density, performance, power, manufacturability and design time Fast functional simulation (hw/sw co-simulation) High level synthesis to chip design implementation Formal Verification Mixed-mode simulation Analog/Digital/RF; HW/SW co-simulation 25

26 Opportunities for System Level Design for VDSM SoC System architecture Hardware Synthesis SW-HW Co-SIM Software Development Silicon Implementation ROM DSP SRAM ROM DSP SRAM ROM IP s Chip-1 Audio SRAM SRAM SRAM Video Analog IP s RISC ef ROM Chip-2 Chip-3 26

27 Opportunities for System Level Design for VDSM SoC System architect design environment for Platformbased designs High level design partitioning and hierarchy Optimization between chip density, performance, power, manufacturability and design time Fast functional simulation (hw/sw co-simulation) High level synthesis to chip design implementation Formal Verification Mixed-mode simulation Analog/Digital/RF; HW/SW co-simulation VDSM-aware architectures: Interconnect Power Manufacturability 27

28 Interconnect-Aware System Architecture Minimize Global Interconnections Because interconnection dominates VDSM physical design, a minimum of global interconnection should be planned at architecture level For instance, serial data transfer, hierarchical partitioning and other techniques should be used to reduce the amount of global interconnect required 28

29 Interconnect-Aware System Architecture (cont.) Minimize Global Interconnections Example massively parallel architecture, with small, highly connected blocks Unable to perform hierarchical design due to interconnect count driving block sizes, resorted to fully-flat physical implementation 29

30 Interconnect-Aware System Architecture (cont.) Minimize Global Interconnections (cont) Example (cont) Extreme difficulty in generating physical design which could accommodate timing and area needs 30

31 Power-Aware System Architecture General-purpose vs application-specific hardware Dynamic power control with flexible block shut-down and restart Careful partitioning Selection of appropriate shut-down/restart sequence Data retention requirements Memory selection & partitioning Break memory space into smaller memory sections Less capacitance per bit Opportunity to power-down memories in unused address space 31

32 Power-Aware System Architecture (cont.) Dynamic P C*Vdd 2 * F Frequency Scaling Reduce frequency when performance requirements can be lowered Results in linear reduction in Dynamic Power Voltage Scaling Reduction of supply voltage when performance requirements are reduced Results in quadratic reduction in Dynamic Power 32

33 Power-Aware System Architecture (cont.) Adaptive Voltage Scaling (AVS) V DD System Processor Adaptive Power Controller Clock Management V DD_OK Performance Monitor AVS Voltage Management Companion Energy Management Power Supply APC Controller Interface Interface SOC 33

34 Power-Aware System Architecture (cont.) Provides Process and Temperature Compensation Power vs. Frequency and Temperature Fixed Voltage 85C 25C -40C 25% savings Process Compensation Temperature Compensation 63% savings Adaptive Voltage 85C 25C -40C -40C (Dynamic P C*Vdd2 * F) 34

35 Power-Aware System Architecture (cont.) Static P Ioff Exp ( C*Vt) Threshold Scaling Apply back-bias voltage to NMOS/PMOS transistors to increase Vt and reduce static leakage VDD VSS A P-well Y VDD N-well N-well N+ N+ P+ P+ P+ N+ A Y P-well N-well P-well Deep N-well N-well VSS P-sub 35

36 Power-Aware System Architecture (cont.) Static power savings vs Threshold Scaling Power Savings(%) after applied BB for P & N Power savings(%) P & N Back Bias Voltages(mV) pwr savings(%) 36

37 Power-Aware System Architecture (AVS/ATS System) Example showing multiple domains Needs proper design partitioning, interface handling, defined performance modes 37

38 Manufacturability-Aware Architecture DFT: Test plan executed at system level design E.g. decomposing complex systems into testable partitions with appropriate access Adaptive system designs capable of working with a circuit or parametric defect Examples include using error-correcting encoding and system calibration schemes Fault-tolerant systems using various techniques Redundancy Error-correcting encoding schemes Shadow memories (RAID) Parallel computation (2 out of 3) 38

39 Chip Level Design for SoC SoC Chip level design consists of logic, circuit and physical design Logic design is the process of creating gate-level representations of RTL (from system-level designs) Circuit design creates gates or design libraries (standard cells, memories, IO s) & analog functional blocks such as PLL s, converters etc. Physical design creates the layout of SoC by means of floorplanning, P&R) that meets manufacturing spec. The recent paradigm for chip level design is Top-down & hierarchical, which is likely to persist in the future For TFM s the main focus is on correct-by-construction which needs to progress in greater pace 39

40 Correct-by-Construction TFM Correct-by-construction TFM s require close linkage between logic, circuit & physical design, and eventually system-level design An example: interconnect-driven chip design > 0.25um Synthesis 0.25 & 0.18um Synthesis < 0.18 um Timing-driven Synthesis Placement Route Post-layout analysis Timing-driven Placement Timing-driven Route Post-layout analysis Timing-driven Placement Timing-driven Route Post-layout analysis 40

41 Opportunities for Chip-Level VDSM designs Design productivity Closer linkage to system-level design Logic optimization (logic) Formal & equivalency checks (logic, circuit) Analog synthesis & behavioral modeling (logic, circuit) Hierarchical designs with awareness of noise, x talk, power, yield, reliability, and testability (logic, circuit, physical) 41

42 VDSM-Aware Hierarchical Design Methodology Hierarchical design methodology has greatly improved design productivity E.g. interconnect (or timing-closure) is being solved hierarchically However, there is no solid solution for other VDSM effects such as noise, x talk or power A B C A1 A1 A2 Need to have attributes for noise, x talk & power, and need to have a methodology to pass these attributes to every level of the hierarchy A11 A12 A11 A11 Block A Block A1 42

43 Opportunities for Chip-Level VDSM designs Design productivity Closer linkage to system-level design Logic optimization (logic) Formal & equivalency checks (logic, circuit) Hierarchical designs with awareness of noise, x talk, power, yield, reliability, and testability (logic, circuit, physical) Analog synthesis & behavioral modeling (logic,circuit) Power consumption TFM s for voltage/threshold scaling architectures such as AVS/ATS (logic, circuit, physical) Innovative low power circuits (circuit) Level shifter (circuit) Designs which utilize Mixed-Vt, Mixed-Tox, and Multi-Vdd techniques simultaneously (circuit, physical) 43

44 Design with Multiple-Vt/Tox Devices To address leakage issue, the latest process technologies offer devices with multiple threshold voltage (Vt) and/or multiple gate oxide thickness (Tox) High-Vt devices have less leakage current Thicker Tox devices have less leakage current With proper TFM development, power & performance can be optimized with mixed-vt & mixed-tox devices coexisting in the same design Utilize higher Vth or thicker Tox devices when timing is not critical 44

45 Opportunities for Chip-Level VDSM Designs (cont.) Manufacturability Non-intrusive Logic BIST with advanced fault models such as x talk, path-delay, noise (logic, circuit, physical) Analog/MS & DC BIST (logic, circuit) BIST technology with self-repair (logic, circuit) Fault-tolerant designs such as ECC (logic) On-chip S/W or H/W reconfiguring (logic, circuit, physical) Automatic insertion of redundancy (logic, circuit) VDSM-aware chip implementation & analysis for DFM (logic, circuit, physical) 45

46 VDSM-aware Correct-by-Construction Having VDSM-aware hierarchical design methodology, the correct-by-construction chip design implementation can then be extended to other VDSM effects such as noise and x talk Timing-driven Synthesis Timing-driven Placement VDSM-driven Synthesis VDSM-driven Placement Interconnect Noise X talk Yield optimization Redundancy insertion Timing-Driven Route Post-layout analysis VDSM-driven Route Post-layout analysis functional Timing Power Yield Reliability 46

47 Opportunities for Chip-Level VDSM Designs (cont.) Manufacturability Non-intrusive Logic BIST with advanced fault models such as x talk, path-delay, noise (logic, circuit, physical) Analog/MS & DC BIST (logic, circuit) BIST technology with self-repair (logic, circuit) Fault-tolerant designs such as ECC (logic) On-chip S/W or H/W reconfiguring (logic, circuit, physical) Automatic insertion of redundancy (logic, circuit) VDSM-aware chip implementation & analysis for DFM (logic, circuit, physical) TFM s to address process variability such as statistical modeling and adaptive circuit (circuit, physical) 47

48 Design Margin vs Process Variability It is more difficult to over-design given greater variability in VDSM processes Need technology to properly design to the statistically probable limits of the design constraints, not a all-worstcase scenario NVTX EDR limits 3-sigma Model corners PVTX 48

49 Summary Design productivity, power consumption and design for manufacturability are the major challenges in designing SoC with VDSM technologies. These challenges are slowing down the adoption of the newest process technologies To address these challenges, innovative ideas in every level of design are needed Design TFM s for system-level and chip-level for VDSM are evolving, but they are still in their infant stage. Continued R&D in these two areas are required 49

50 Summary (cont.) SoC design start will continue to be moved to higher design level Platform-based design methodology is the next design paradigm for SoC designs More tightly-coupled interaction between each level of design is required to insure correct-byconstruction techniques 50

51 Thank You 51

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