Contents Introduction Sparse Feature Extraction and Matching

Transcription

1 Contents 1 Introduction Motivation Image Domain Warping Thesis Overview Prior Work Contributions List of Publications Sparse Feature Extraction and Matching Introduction Related work Algorithmic Details of SKB Interest Point Detection Descriptor Calculation Descriptor Matching Descriptor Performance Hardware Architecture Image Pyramid and Line Buffer Detection and Extraction Core Descriptor Matching Results ASIC Implementation of the Core FPGA Implementation of the System Summary and Conclusions A Improved Kernels xiii

2 xiv CONTENTS 3 Spatio-Temporal Edge-Aware Filtering Introduction Related Work Edge-Aware Filtering Optimization Problems Temporal Consistency Optical Flow Estimation Features STEA Filtering Pipeline Spatial Filtering of Dense Data Spatial Filtering of Sparse Data Efficient Formulation of the Spatial Filter Temporal Filtering Temporal Permeabilities and Flow Constancy CPM with Binary Descriptors Binarized Octal Orientation Maps Modifications of CPM and Parametrization Results and Comparisons Implementation and Choice of Parameters Performance of CPM and BOOM Optical Flow Performance Applications and Temporal Consistency Summary and Conclusions A Comparison of BOOM and SKB B A BOOM Feature Extraction Core C MVS with Nearest Neighbour Fields Evaluation of Linear Solvers for IDW Introduction Related Work Preliminaries Linear Systems in Image/Video Processing Matrix Properties in IDW Applications Linear Solver Algorithms Direct Cholesky Solver Incomplete Cholesky Factorization Iterative CG Solver Evaluated Hardware Architectures

3 CONTENTS xv Cholesky Variants Approximate Cholesky Variants Conjugate Gradient Variants Estimation Framework Test Data Generation Runtime, Precision & Activity Power & Area Estimation Evaluation Results Matrix Condition and Solution Accuracy Results Discussion Summary and Conclusions Efficient Resampling for MADs Introduction Background Ideal Single View Resampling Sampling for Multiview Displays Resolution Ratio Practical Multiview Resampling Resampling Artifacts Removing Aliasing Artifacts Evaluation Resampling strategies Discussion Summary and Conclusions Logarithmic Number Units Introduction Related Work Preliminaries LNS Number Representation and Format Arithmetic Operations in LNS Rounding Modes and Precision Cotransformation Architecture Template and Extensions MulDiv and AddSub Preprocessing Blocks Main Interpolator Block

4 xvi CONTENTS LogExp Block Postprocessing Block Trigonometric Functions LNU Generator Polynomial Fitting Error Calculation and Word Width Selection Processor Integration LNU Design Space Exploration Area, Precision and Timing Tradeoffs Function Kernel Performance LNUs in a Larger Context Comparison with Related Work Chip Variants Designed Instruction Level Performance Function Kernel Performance Summary and Conclusions Stereo-to-Multiview Prototype Introduction Background and Related Work Multiview Synthesis Methods Image Features and Saliency Estimation Linear Solvers Resampling for Multiview Displays Real-time Systems and HW Architectures Algorithmic Flow Sampling Lattices, Domains and Warps Video Analysis Warp Generation Warp Interpolation and Rendering Hardware Architecture Interfaces Schedule and Memory Maps Stereo Video Analysis Warp Generation Interpolation, Rendering and Accumulation Results Multiview Synthesis Results

5 CONTENTS xvii Functional Characteristics and Performance ASIC Complexity and Power Estimates Comparison with Related Work Summary and Conclusions Conclusions Summary of Main Results General Observations on Efficiency Outlook and Future Work A Chip Gallery 229 B Notation and Acronyms 241 Bibliography 247 Curriculum Vitae 271