Reconfigurable HDL Library Development Platform for Arithmetic and Matrix Operations

Transcription

1 IMPLEMENT Tanslate Map Place & Route Intenational Jounal of Compute Applications ( ) Reconfiguable HDL Libay Development Platfom fo Aithmetic and Matix Opeations Semih Aslan Ingam School of Engineeing Texas State Univesity S. Macos, Texas, 78666, USA ABSTRACT Embedded systems used in eal-time applications equie design tools that could be costly and may have long veification cycles. Many design tools use pedefined libaies and costly IPs duing these design and veification cycles, and most of these libaies and IPs ae static and difficult to modify. Many design equiements ae changed duing o afte design and veification cycle, and designes need to addess these changes and modify the system. This could be moe time consuming due to veification cycle and static libaies. It is impotant to have dynamic libaies that could be modified and econfigued based on the applications. This wok ceates econfiguable aithmetic design blocks that could be used fo aithmetic and matix opeations. The econfigued libay development system modifies the equied libay elements using Pel scipting language and veifies them on-the-fly using MATLAB. The development tool impoves design time and educes the veification pocess, but the key point is to use a unified design that combines some of the basic opeations with moe complex opeations to educe aea and powe consumption. The esults indicate that using the econfiguable development tool educes veification time and inceases the poductivity. These libaies include stuctual Veilog HDL codes, testbench files, and MATLAB scipt files fo local customization. Even though the econfiguable HDL libay is used fo FPGA design flow, it could be easily modified fo VLSI design flow. Geneal Tems FPGA, Veilog HDL, Pel, MATLAB Keywods Hadwae optimized, HDL, High Level Synthesis, MATLAB, Optimized Hadwae, Pel, Powe Efficient, Reconfiguable, RTL, Veilog HDL.. INTRODUCTION Designing complex systems such as image and video pocessing, compession, face ecognition, object tacking, multi-standad CODECs, and HD decoding schemes equies many basic and complex aithmetic blocks and a long veification pocess []. These complex designs ae based on many Input/put, pocessos, bus intefaces, memoies and sensos. Many times, these systems can be designed as a single chip that is known as System-On-Chip (SoC) []. Many designes use RTL design flow when SoC ae designed and veified. These design tools use design libaies that ae mostly static and difficult to configue and veify. When a new o modified libay element is needed, designes ty to ceate new libay elements fom scatch o ode new libaies fom the vendo. These could be time consuming and costly fo the designes. Classic design flow that uses static libay and RTL design flow [] [] fo both FPGA and ASIC is shown in Figue. Algoithm RTL Libay Logic Synthesis Fomal Poof Timing Fig : FPGA RTL level synthesis flow Bit File An algoithm can be conveted to RTL using the behavioal desciption model, pedefined libaies and IP coes. Afte completing this RTL code, fomal veification must be done befoe implementation. Afte implementation of the RTL code, timing veification needs to be done fo pope opeation. When a equied change o futue modification is equied by the costume, the design needs to go though same synthesis flow. This dastically inceases time-to-maket (TTM) if new libaies need to be used, because it will equie evey pat of the design to be veified. This will cause longe veification peiod of the design and it will incease design cost. The design and veification of the libaies and oveall design shown in Figue can take up 4-5% of the Time to Maket (TTM). The RTL design that is shown in Figue becomes costly and impactical fo lage system change and updates. Fo example, a base system design team that is woking on 3G wants to move to 4G design using FPGA can have shote TTM if the team uses econfiguable pe-veified libaies [3]. One method to ovecome this poblem is to intoduce high level languages to the design cycle. Because of the extensive wok done in Electonics System Level Design (ESLD), HW/SW co-design of a system and High Level Synthesis (HLS) [3][4] ae integated into FPGA and ASIC design flow. RTL desciption of a system can be implemented fom a behavioal desciption of the system in Pel, C, Python and MATLAB [5]. This will esult in a faste veification pocess and shote TTM. This HLS idea focuses on design as whole. Some designes want to contol the design and make cetain changes in HDL code, but this could have a low possibility whee HLS is used. The poposed design uses the scipting language Pel to ceate and MATLAB to veify each equied libay file. This integation is shown in Figue, and it intoduces MATLAB and Pel into synthesis flow and veifies all the libay design files. Each libay element can be ceated and tested independently without inteupting the design and veification flow. This enables softwae designes to join the design pocess duing hadwae design and veification. Afte the veification pocess, the design can be implemented using FPGA synthesis tools. 4

2 IMPLEMENT Tanslate Map Place & Route Intenational Jounal of Compute Applications ( ) Algoithm Fomal Poof Pel MATLAB Libay RTL Timing Bit File USER CONSTRAINTS PERL Scipt Veilog HDL Design File Veilog HDL Testbench File Fig. : Poposed FPGA high level synthesis flow The next section will descibe the poposed design and libay geneation pocess. Section 3 will focus on the desciption of each block, and the conclusion will descibe futue wok and impovements.. PROPOSED DESIGN The poposed design focuses on designing a econfiguable libay that could be used fo a new o updated design. The TTM will be shote with a design pinciple simila to HLS, as explained above. The main wok focuses on designing libay blocks that could be used and modified based on custome need. The libay design will be done using Pel command line inteface. The cuent libay development platfom suppots; OS platfoms such as Windows, Linux and Mac OS X Customized ange and accuacy FPGA o ASIC suppot Vendo based IP coe integation Aea and powe optimized Use defined module and file names Veilog HDL suppot n-bit Fixed point numbe system (<n<9) Signed o unsigned numbe systems Testbench geneation Automated testbench with MATLAB Modelsim.do file fo fast automation Eo compaison with MATLAB Use defined test data option The development platfom ceates the libay blocks fo desied opeations such as addition, multiplication, etc. based on use constaints. The poposed design is explained and synthesized and implemented with Xilinx FPGAs [6] fo opeational veification. Libay geneation and veification flow is shown in Figue 3. MATLAB Scipt File Iveilog/ MODELSIM Veification and Eo Files Fig. 3: Libay geneation and veification flow The poposed development platfom is witten in Pel scipting language. The platfom accepts use constaints such as file name, numbe of input bits, test vecto numbe, etc. It geneates the Veilog HDL, testbench, MATLAB and batch files, and executes the batch file. The batch file opens MATLAB to geneate testvectos and Modelsim o Iveilog fo functional veification. Afte unning Modelsim o Iveilog, the output files ae geneated fo veification. These files ae tansfeed into MATLAB to compae with the expected esults, and MATLAB displays the eo plots. This method can design and veify the design much shote time, and allows the use to pefom a full veification (veification time can incease based on platfom and compute specs) o specify his/he testvectos fo custom veification. 3. BUILDING BLOCKS Basic aithmetic and logic opeations such as addition, subtaction, multiplication, memoy elements, egistes, multiplexes, demultiplexes, s and s complements systems ae building blocks of most of the systems in DSP and communication systems. By using these basic building blocks, moe complex and useful blocks can be designed. Some of these aithmetic building blocks ae division, squae oot, invese squae oot and CORDIC (used to design tigonometic, hypebolic and exponential functions) and some matix opeations such as addition, and subtaction and multiplication. These libay blocks that ae geneated by the econfiguable development tool ae shown in Figue 4 below. In this section, these libay blocks and thei constuction by the development tool is discussed in detail. Due to the simplicity and extensive eseach done on memoy elements, multiplexes, demultiplexes, shiftes, complement systems, addes and multiplies ae not discussed in detail hee. Hadwae implementation of complex aithmetic opeations and elementay functions is moe difficult than hadwae implementation of basic aithmetic opeations. Thee ae a few algoithms used on today s computes to implement these functions. This chapte includes a bief desciption of these algoithms.the design platfom uses some of these algoithms to implement these elementay functions, as well as some of the basic aithmetic opeations. 4

3 Intenational Jounal of Compute Applications ( ) In In In In In In Shift In In In In In In In In In In In In Mux DeMux In Complement Data_In Memoy Addess CORDIC Matix Add/Sub Matix Multiplication Date_ These algoithms can pefom diffeently based on the equied sub functions. As a futhe example, division using a CORDIC algoithm may equie less hadwae [7] but it may be slow due to linea convegence; on the othe hand, division by the Newton-Raphson [8] method may be faste but it may equie moe hadwae. 3. Addition/Subtaction Thee ae two adde systems designed by the development system. Depending on speed o aea, the development tool chooses Cay-Lookahead Adde (CLA) o Ripple-Cay Adde, espectively. Based on the selection, the subtaction system is designed with the adde. 3. Multiplication The development tool can design sign and unsigned type multiplies based on Aay and Booth multiplies. Based on the design platfom, uses can choose thei multiplies fom an IP coe povided by the manufactues. This may incease the oveall pefomance and suggested method whee IPs ae available. The Pel code that geneates any bit signed multiplie [9][] Veilog is given in Listing below. Listing. Multiplie Veilog file geneation. #!/us/bin/pel # Signed Multiplie use wanings; use stict; my $multiplie; pint "Please Ente Module Name fo Signed Multiplie :"; chomp ($multiplie = <STDIN>); my $bit; pint "Please Ente numbe of bits fo Multiplie(x) :"; chomp ($bit = <STDIN>); my $bit; pint "Please Ente numbe of bits fo Multiplicand (y) :"; chomp ($bit = <STDIN>); my $i; my $taget; while () { my $taget = $multiplie; chomp $taget; if (-d $taget) { pint "$taget is a diectoy. This might ceate poblem\n"; if (-e $taget.".v") { pint "$taget.v aleady exists. \n"; pint "Ente '' to wite to a diffeent name : "; pint "\nente 'o' to ovewite \n"; pint "Ente 'b' to back up to $taget.old\n"; my $choice = <STDIN>; chomp $choice; if ($choice eq "") { elsif ($choice eq "o") { Fig. 4: The econfiguable libay blocks unless (-o $taget.".v") { pint "Can't ovewite $taget.v, it's not yous.\n"; unless (-w $taget.".v") { pint "Can't ovewite $taget: $!\n"; elsif ($choice eq "b") { if ( ename($taget.".v",$taget.".old") ) { pint "OK, moved $taget.v to $taget.old\n"; else { pint "Couldn't ename file: $!\n"; else { pint "I didn't undestand that answe.\n"; last if open OUTPUT, "> $taget.v"; pint "I couldn't wite on $taget: $!\n"; # cannot wite. pint OUTPUT "/*\n"; pint OUTPUT "Name:Signed Multiplie\n"; pint OUTPUT "Designe:Semih Aslan\n"; pint OUTPUT "*/\n"; pint OUTPUT "module $multiplie (x, y, poduct);\n"; pint OUTPUT "paamete M = ",$bit-,"; \n"; pint OUTPUT "paamete N = ",$bit-,"; \n"; pint OUTPUT "input [M-:] x;\n"; pint OUTPUT "input [N-:] y;\n"; pint OUTPUT "output [M+N-:] poduct;\n"; pint OUTPUT "wie sum [M-:][N-:];\n"; pint OUTPUT "wie cay [M-:][N-:];\n"; pint OUTPUT "genva i, j;\n"; pint OUTPUT "geneate fo (i=; i<n; i = i +) begin:\n"; pint OUTPUT " signed_multiplie\n"; pint OUTPUT " if (i==)\n"; pint OUTPUT " fo (j=;j<m;j=j+) begin: fist_ow\n"; pint OUTPUT " if (j==m-)\n"; pint OUTPUT " assign sum[j][i] =!(x[i]&y[n-]),\n"; pint OUTPUT " cay[j][i]=;\n"; pint OUTPUT " else\n"; pint OUTPUT " assign sum[j][i]=x[j]&y[i],\n"; pint OUTPUT " cay[j][i] = ; end\n"; pint OUTPUT " else if (i==n-)\n"; pint OUTPUT " fo (j=;j<m;j=j+) begin: last_ow\n"; pint OUTPUT " if (j==m-)\n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =(x[m-]&y[n- ])+cay[j][i-]+cay[j-][i];\n"; pint OUTPUT " else if (j==)\n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =!(x[m- ]&y[j])+sum[j+][i-];\n"; pint OUTPUT "else \n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =!(x[m- ]&y[j])+sum[j+][i-]+cay[j-][i];end\n"; pint OUTPUT "else \n"; pint OUTPUT " fo (j=;j<m;j=j+) begin : est_ows\n"; pint OUTPUT " if (j==)\n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =(x[j]&y[i])+sum[j+][i- ];\n"; 4

4 Intenational Jounal of Compute Applications ( ) pint OUTPUT " else if (j==m-)\n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =!(x[i]&y[n- ])+cay[m-][i-]+cay[j-][i];\n"; pint OUTPUT "else \n"; pint OUTPUT " assign {cay[j][i],sum[j][i] =(x[j]&y[i])+sum[j+][i- ]+cay[j-][i];end\n"; pint OUTPUT "end endgeneate\n"; pint OUTPUT "geneate fo (i=;i<n;i=i+)\n"; pint OUTPUT " begin: poduct_lowe_pat\n"; pint OUTPUT " assign poduct[i] = sum[][i];\n"; pint OUTPUT " end endgeneate\n"; pint OUTPUT " geneate fo (i=;i<m;i=i+)\n"; pint OUTPUT " begin: poduct_uppe_pat\n"; pint OUTPUT " assign poduct[n-+i] = sum[i][n-]; \n"; pint OUTPUT " end endgeneate\n"; pint OUTPUT " assign poduct[m+n-] = cay[m-][n-] + 'b; \n"; pint OUTPUT " endmodule \n"; 3.3 Division/Squae Root/Invese Squae Root The development tool can design division, squae oot, and invese squae oot hadwae and thei testbenches individually o all togethe using the hadwae euse pinciple. These building blocks ae designed using Newton-Raphson [9][][][] and CORDIC algoithms [3][4][5]. The CORDIC algoithm is used in many diffeent aithmetic and elementay functions except fo division, squae oot and invese squae oot. The division opeation can be witten as: N = D. Q + R () whee N is dividend, D is diviso, Q is quotient, R is emainde and R < D.ulp and sign (R) = sign(n). The unit in the last position (ulp) epesents the lowest tem whee ulp = fo intege numbes and ulp = (adix)-n fo n-bit factional numbes [6] Newton-Raphson Division The Newton-Raphson method shown in Equation () is a well-known technique to find the oot of nonlinea functions. This oot can be calculated using an initial value by appoaching the oot quadatically [8][9][7][8]. The accuacy of the division opeation doubles in each iteation. The initial value estimation can educe the iteation numbe and incease accuacy. X i+ = X i f(x i) f (X i ) The function f X = D can be defined to calculate X X i+ = whee D is the diviso. Afte applying f X and D f X to Equation (), X i+ = can be calculated as D X i+ = X i ( DX i ) (3) Afte n th iteation, the value of X i+ conveges to /D and the quotient can be calculated as Q = N (/D). Design accuacy and eo can be impoved by inceasing the numbe of iteations and bette estimate of initial value [9]. The hadwae implementation of Newton-Raphson division and its iteation steps ae descibed in Figue 5 and Table, espectively. () D N Mux_A Mux_B X Mux_C B 's Comp. x Fig. 5: Newton-Raphson division method A Table below shows the opeation of the division block. In cycle, pe-detemined values of initial appoximation X and D ae fetched into the multiplie. The poduct tem is calculated and its twos complement is stoed in B. In cycle, this complemented value is multiplied by X and the esult is stoed in A as X. Afte thee iteations o six clock cycles, the value of X 3 conveges to /D. Afte calculation of /D, the quotient can be calculated as shown in cycle 7 by multiplying X 3 by N. This algoithm and its pefomance depend on the numbe of iteations and initial appoximation. Calculation of.85/.5 when X =.5 and X =.75 fo diffeent iteations ae shown in Figues 6 and 7, espectively. Opeation Cycle Table. Newton-Raphson division cycles. Mux A Mux B Mux C A B --- -D. X X D. X 4 X D. X 6 X N.X X i+ 43

5 Intenational Jounal of Compute Applications ( ) 3.3. Newton-Raphson Squae Root and Invese Squae Root Hadwae implementation of squae oot and invese squae oot ae possible using Newton-Raphson algoithms that ae simila to division opeations. This makes it possible to have unified division, squae oot and invese squae oot opeations. Invese squae oot opeations can be geneated using the Newton-Raphson algoithm. The function f X = X can be defined to calculate X D i+ =. Afte applying D f X and f X to Equation (); X i+ = X i (3 DX i ) (4) Fig. 6: Calculation of.85/.5 when X =.5 Afte nth iteations, the value of X i+ will convege at the squae oot of D. Calculations of the squae oot can be done by multiplying the final value of Equation (4) by D. The hadwae implementation of Newton-Raphson squae oot and invese squae oot methods and thei iteation steps ae descibed in Figue 9 and Table, espectively. C Shift_R Add 's Comp. X Mux_B D Mux_A Mux_C x A B Fig. 7: Calculation of.85/.5 when X =.75 The development system detemines the numbe of iteations and calculates the optimal initial value based on that iteation as shown in Figue 8 below. Fig. 8: Calculation of.85/.5 fo diffeent initial values. Fig. 9: Newton-Raphson invese-sqt and sqt methods. Table. Newton Raphson invese sqt and sqt cycles. OC A B C X D.X (3 - D.X ) 3 - X.(3 - D.X ) - X.(3 - D.X ) X 5 D.X X (3 - D.X ) 6 - X.(3 - D.X ) - X.(3 - D.X ) X 8 D.X X (3 - D.X ) 9 - X.(3 - D.X ) - X.(3- D.X ) --- D.X Table above shows the opeation of the invese squae oot and squae oot blocks. In cycle, X is calculated. This value is stoed in A. In cycle, X is multiplied by D and the esult D X is stoed in A and - (3 - D X ) is stoed in C. In cycle 3, - (3 - D X ) is multiplied by X and esult - X (3 - D X ) is stoed in A and B. This is the end of the fist iteation. istes A and B ae holding the value of X that will be used in the second iteation. Iteations and 3 ae done in cycles 4 though 9, and 44

6 Intenational Jounal of Compute Applications ( ) the final esult X 3 will convege into calculated by multiplying D D. D. In cycle, D is 3.4 Sine and Cosine Implementations Sine and cosine functions can be implemented using the CORDIC algoithm. The CORDIC (COodinate Rotation DIgital Compute) algoithm was fist descibed in 959 by Jack E. Volde [][3] to eplace the analog esolve in the B-58 bombe s navigation system. Since then, quite a bit of eseach has been done on the topic. This algoithm is used today in digital filtes, FFT, DFT, Kalman filtes, adaptive lattice stuctue, linea algeba applications, singula value decomposition (SVD) calculations, Given s otation and QRD-RLS filteing []. The CORDIC algoithm is based on two modes; vectoing and otation. This algoithm and its deivation ove linea, cicula and hypebolic coodinate systems can compute many elementay functions descibed above. Let us assume that point A otates to B by an angle of otation angle θ, as shown in Figue. This will ceate a new point B(X,Y ), and the elation of the new point B based on pevious point A and the otation angle θ [7][4][5][]. R Y Y x = R. cos β (5) y = R. sin (β) (6) θ R β X B(X,Y ) R X A(X,Y) Fig. : Rotation of vecto A(x,y) to B(x,y ) x = R. cos θ + β (7) y = R. sin (θ + β) (8) Using the tigonometic popeties; sin θ + β = sin θ cos β + cos θ sin β (9) cos θ + β = cos θ cos β sin θ sin β () Putting (9) and () in (7) and (8) x = R. cos θ cos β R. sin θ sin β () y = R. sin θ cos β + R. cos θ sin β () Putting (5) and (6) in () and () x y = cos θ tan θ tan θ x = cos θ x y. tan θ x y (3) (4.a) y = cos θ x. tan θ + y (4.b) In this iteation, the value of tan θ can be chosen in tems of powe of. This will make it easy to implement as hadwae because i is simply an L-R shift. This tansfomation can be done by a sequence of smalle angle otations ( θ i ) in which, n θ = θ i And by using this Equation [3] can be witten as; x i+ y = cos θ i sin θ i i+ sin θ i cos θ i i (5) x i y i (6) tan θ i = i (7) θ i = tan i (8) In addition, the value of the poduct of the cos θ will be constant. This value is known as K i (scaling facto). K i = K i = n i= n i= cos θ i cos tan i (9) () Using the tigonometic popety; cos tan α = () + α Equation () scaling facto would be n K i = i= + i () This scaling facto value will be constant fo lage n (iteation numbe). Using the Equations (8) and () in Equation (6) the following may occu. and x i+ = K i. x i y i ( i ) (3) y i+ = K i. y i + x i ( i ) (4) x i+ = K i. x i d i. y i ( i ) (5) y i+ = K i. x i + d i. x i( i ) (6) The otation of the angle must be updated. This will intoduce a new set of equations: z i+ = z i d i. tan ( i ) (7) Values fo tan ( i ) can be stoed in the memoy. Vaiable d i is the diection of the otation and its value depends on z i. This may be epesented as shown below: d z i i (8) z i < Afte the desciption of the vectoing mode opeation, a geneal desciption of CORDIC algoithm fo linea, cicula and hypebolic coodinates using vectoing and otation modes can be given as shown below [4] []. z i+ = m = cicula coodinates linea coodinates hypebolic coodinates (9) x i+ = x i m i y i i (3) y i+ = y i + i x i i (3) z i i tan i z i i tanh i z i i i if m = if m = if m = (3) 45

7 . Intenational Jounal of Compute Applications ( ) Table 3. CORDIC shift sequences and scaling facto Coo. System M Shift Sequence S m,i Convegence α max Scale Facto K m (n ),,,,i, ,,,i+,... -,,3,4, Using these Equations MATLAB code to fo design and veification ae shown in Figues, and 3, espectively. Table 4. CORDIC pocesso fo thee coodinate systems Coo Sys Rot. / Vec. Rot. Vec. Initializing X = X S Y = Y S Z = β X =/K,n Y = Z = β X = X S Y = Y S Z = β Result Vectos X n = K,n (X S cos(β) - Y S sin(β)) Y n = K,n (Y S cos(β) + X S sin(β)) Z n = β X n = cos(β) Y n = sin(β) Z n = X n = K,n (sgn(x )(sqt(x +y ) Y n = Z n = β+tan - (Y S /X S ) Fig. : MATLAB sine(θ) and cos(θ) calculations Rot. X = X S Y = Y S Z = Z S X n = X S Y n = Y S + X S Y S Z n = Vec. X = X S Y = Y S Z = Z S X n = X S Y n = Z n = Z S + Y S / X S - Rot. X = X S Y = Y S Z = β X =/K -,n Y = Z = β X n = K -,n (X S cosh(β) + Y S sinh(β)) Y n = K -,n (Y S cosh(β) + X S sinh(β)) Z n = X n = cosh(β) Y n = sinh(β) Z n = - Vec. X = X S Y = Y S Z = β X n = K,n (sgn(x )(sqt(x +y ) Y n = Z n = β+tan - (Y S /X S ) Using Table 3 and Table 4, sin(θ) and cos(θ) values can be calculated. The cicula coodinate otation mode CORDIC can be used [4][]. Fig. : Sin(θ) and cos(θ) values between < θ <.5 x i+ = K. x i i y i i (33) y i+ = K. y i + i x i i (34) z i+ = K. z i i tan i (35) To stat the iteation, the following initial values need to be assigned. K =.6676 (36) x = K =.6676 (37) y =, (38) z = θ (39) Fig. 3: Sin(θ) and cos(θ) values between < θ < Sinh, Cosh and e (x) Implementations Sinh and Cosh functions can be implemented using the CORDIC povided above in Table 3 and 4. To calculate sinh(θ) and cosh(θ) values, the hypebolic coodinate otation mode CORDIC can be used [4][]. x i+ = K. x i + i y i i (4) 46

8 . Intenational Jounal of Compute Applications ( ) y i+ = K. y i + i x i i (4) z i+ = K. z i i tanh i (4) To stat the iteation, the following initial values need to be assigned. Afte n th (4). K =.8386 (43) x = K =.8386 (44) iteation, and using the Equations (4), (4) and x n = sinh(θ) (45) y = cosh(θ) (46) z = (47) An exponential function can be calculated using (45) and (46). e x = cosh(θ) + sinh(θ) (48). MATLAB epesentation of sinh, cosh, and exponential functions and eo analysis ae shown in Figues 4, 5, and 6, espectively. Fig. 4: MATLAB code fo sinh(θ), cosh(θ) and exponential function calculations Fig. 6: Sinh(θ), cosh(θ) and e θ values between < θ < 3.6 Matix Opeations The libay design platfom can ceate libay elements fo some basic matix opeations such as addition, subtaction and multiplication. The libay design matix hadwae and veification as same as explained above in Figue Matix Addition/Subtaction Hadwae implementation of matix addition is done as shown in Equations (49) and (5), espectively. C = A + B (49) c i,j = a i,j + b i,j whee i, j =,,, n (5) The conventional design is easy to undestand and implement. The design platfom uses the equation that is given in Equation (5) to calculate all elements of matix C. The matix addition/subtaction block is shown in Figue 7 below. Memoy b, a, b, a, n n n n n n n n n c, c, c i,j b i,j a i,j Memoy Fig. 5: Eo analysis of sin(θ) and cos(θ) Fig. 7: Matix addition/ subtaction block 3.6. Matix Multiplication Matix multiplications [8][] ae heavily used in many signal and image pocessing applications, such as adaptive beamfoming [6][8] and multiple-input-multiple-output (MIMO) systems [8], and factoizations [][][3][4] such as QR factoization and DCT. Matix multiplication equies opeation elements (OE) such as addition and multiplication. In a matix multiplication, the numbe of OEs depends on the matix size. The elation between matix size and the numbe of OEs is quadatic. This made it difficult to implement eal time matix multiplication libaies fo lage 47

9 Intenational Jounal of Compute Applications ( ) matices. The design platfom uses taditional matix multiplication to geneate libay element. Matix multiplication of an m matix A and n matix B poduces a m n matix C [5]. a, a, a m, a m, whee; A m, B,n = C m,n (5) b, b,n = b, b,n c i,j = k= a i,k b k,j c, c,n (5) c m, c m,n (53) This matix multiplication equies m n [M+(-)A] aithmetic opeations, whee M is fo multiplie and A is fo adde. Fo example; multiplication of A 4,3 and B 3,6 esults in C 4,6. This opeation equies 7 multiplication and 48 addition opeations. This shows that a n n matix multiplication equies n 3 multiplications and n (n ) additions. The numbe of multiplications in the matix multiplication opeation inceases by an exponent of thee (n 3 ) with the matix size. The hadwae ealization of a matix multiplication focuses on designing c i,j due to the paallel natue of the system. In geneal, calculation of c i,j is done using a bottom-up appoach. The tem c i,j in Equation (53) can be witten as; c i,j = a i, b,j + a i, b,j + + a i,n b n,j (54) Due to the matix size choice of n = k, the Equation 54 can be witten as c i,j = d + d + + d t (55) This d t calculation block shown in Figue 8Fig is one of the most basic and impotant blocks in matix multiplication. Any matix multiplication can be done using only one of these blocks, an adde and ounding scheme. Howeve, this is impactical fo lage matices due to slow oveall opeation and incease in eo boundaies. Thee ae many diffeent designs [6] that use diffeent numbes of d t calculation blocks to impove speed. The platfom geneates the libaies based on the smalle block that is shown in Figue 8 above and using this block lage blocks can be ceated as shown in Figue 9 below. Lage matix multiplications can be ealized by using these blocks. A 3x3 matix multiplication design block is shown in Figue below. a i,t- b t-,j a i,t b t,j iste iste iste iste iste iste Fig. 9: Realization of x block iste x d t whee; d t = a i,t b t,j + a i,t b t,j t n (56) The hadwae ealization of Equation (56) is shown in Figue 8. a i,t- a i,t- b t-,j b t-,j Memoy a i,t d t Memoy b t,j a i,t b t,j Fig. 8: Hadwae ealization of d t 48

10 Ci,j Intenational Jounal of Compute Applications ( ) a i,3 a i,3 a i,3 a i,9 a i,8 a i,7 a i,6 a i,5 a i,4 a i,3 a i, a i, a i, a i,9 a i,8 a i,7 a i,6 a i,5 a i,4 a i,3 a i, a i, a i, a i,9 a i,8 a i,7 a i,6 a i,5 a i,4 a i,3 a i, a i, b 3,j b 3,j b 3,j b 9,j b 8,j b 7,j b 6,j b 5,j b 4,j b 3,j b,j b,j b,j b 9,j b 8,j b 7,j b 6,j b 5,j b 4,j b 3,j b,j b,j b,j b 9,j b 8,j b 7,j b 6,j b 5,j b 4,j b 3,j b,j b,j x x x x x x x x x x x x x x x x d6 d5 d4 d3 d d d d9 d8 d7 d6 d5 d4 d3 d d x 8 8 x 8 8 x 8 8 x x 6 6 x x 3 4. CONCLUSION An aea efficient, econfiguable HDL libay development platfom fo Aithmetic and Matix Opeations is designed fo digital design and veification. The platfom geneates dynamic design libaies and veification files to impove design and veification of oveall systems. Based on design complexity and equied changes, TTM can be impoved by up to 6%. Even though this platfom is not tue HLS, it could be consideed as hybid HLS. Any designed system can be econfigued at any time in any way using the dynamic libaies without going though the same design and veification hassle. MATLAB-based veification makes it possible to use all the featues of MATLAB fo faste and moe efficient veification. The Pel-based design makes it possible to use all impotant text manipulations in Pel language. Even though command line use inteface is use fiendly, it ceates some hassle fo uses when the libay size inceases. The futue development platfom will integate a use fiendly GUI using Pel/Tk. Anothe futue goal is to make this platfom totally open souce by using only Iveilog and eplacing MATLAB with Octave. In addition, cuent matix libaies ae limited to addition, subtaction and matix multiplication. The futue development platfom will include some impotant matix factoizations such as QR and LU factoizations, and Stassen based matix multiplication fo aea optimization. 5. ACKNOWLEDGMENTS Autho thanks to Xilinx [6] and MATLAB fo thei suppot fo this eseach. 6. REFERENCES [] Andieux, J., M. Feix, G. Mougues, P. Betand, B. Iza, and V. Nguyen. "Optimum Smoothing of the Wigne Ville Distibution." IEEE Tansactions on Acoustics, Speech, and Signal Pocessing 36.5(987): [] Adle, J., K. Delgado, and B. Rao. "Compaison of Basis Selection Methods." Poceeding of IEEE Asiloma Confeence on Signals, Systems, and Compute Fequency and Time Scale Analysis (996): 5-57 [3] Aslan, S., Ouklu, E., and Saniie J., A high-level synthesis and veification tool fo fixed to floating point convesion, IEEE Intenational Midwest Symposium on Cicuits and Systems,, Pages, Fig. : Realization of 3x3 block [4] Desmoulies, C., Aslan, S., Ouklu E., Saniie, J., Vallina, F.M., HW/SW co-design platfom fo image and video pocessing applications on Vitex-5 FPGA using PICO IEEE Intenational Confeence on Electo/Infomation Technology,, Pages, -6. [5] Chen, W. The VLSI Handbook. Boca Raton: CRC Publishe, 7. [6] Xilinx. (6), [7] Kilts, S. Advanced FPGA Design Achitectue, Implementation, and Optimizations. New Yok: Wiley Inte-Science, 7. [8] Stine, J. E. "Digital Compute Aithmetic Datapath Design using Veilog HDL", Nowell, Massachusetts, Kluwe Academic Publishing, 4. [9] Lin, Ming-Bo, "Digital System Design and Pactices Using Veilog HDL and FPGAs", Singapoe, Wiley Publishing, 8. [] Joseph Cavanagh, " Compute Aithmetic and Veilog HDL Fundamentals ", Boca Raton, FL, CRC Pess, Taylo & Fancis Goup,. [] Flynn, M. J., and S. F. Obeman. "Division Algoithms and Implementations." IEEE Tansactions on Computes 46.8 (997): [] Schulte, M. J., and L. K. Wang. "Decimal floating-point squae oot using Newton-Raphson iteation." Application-Specific Systems, Achitectues and Pocessos (5): [3] Volde, J. "The CORDIC Tigonometic Computing Technique." IEEE Tansactions Electonic Computes 8.3 (959): [4] Stiling, W. C., and T. K. Moon. Mathematical Methods and algoithms fo Signal Pocessing. New Jesey: Pentice Hall,. [5] Andaka, R. "A suvey of CORDIC algoithms fo FPGAs." Poceedings of the 998 ACM/SIGDA sixth intenational symposium on Field pogammable gate aays (998): 9-. [6] Lang, T. M., and D. Ecegovac. Digital Aithmetic. San Fancisco: Mogan Kaufmann, 4. 49

11 Intenational Jounal of Compute Applications ( ) [7] Flynn, M. J., and S. F. Obeman. "Division Algoithms and Implementations." IEEE Tansactions on Computes 46.8 (997): [8] Swatzlande, E.E. J., and W.L.Gallaghe. "Fault- Toleant Newton-Raphson and Goldschmidt Divides Using Time Shaed TMR." IEEE Tansactions on Computes 49.6 (): [9] Oma, J., E. E. Swatzlande J., and M. J. Schulte. "Optimal Initial Appoximations fo the Newton- Raphson Division Algoithm." Spinge-Velag Jounal of Computing (994): [] Dehon, A., and S. Hauck. Reconfiguable Computing The Theoy and Pactice of FPGA-Based Computing. Bulington, Massachusetts: Elsevie, 8. [] Teukolsky, S. A., W. T. Vetteling, B. P. Flanney, and W. H. Pess. "Numeical Recipes: The At of Scientific Computing." Numeical Recipes: The At of Scientific Computing, 3d ed. New Yok, New Yok: Cambidge Univesity Pess, 7. [] Eisman, A. M., I. S. Duff, and J. K. Reid. Diect Methods fo Spase Matices. New Yok, United States of Ameica: Oxfod Univesity Pess, 3. [3] Fujii, A, R Suda, and A Nishida. "Paallel Matix Distibution Libay fo Spase Matix Solves." Poceedings of the Eighth Intenational Confeence on High-Pefomance Computing in Asia-Pacific ion (5): 9-6. [4] Aslan, S., E. Ouklu, and J. Saniie. "Realization of aea efficient QR factoization using unified division, squae oot, and invese squae oot hadwae." IEEE Intenational Confeence on Electo/Infomation Technology (9): [5] Watkins, David S. Fundamentals of Matix Computations, nd ed. New Yok, United States of Ameica: John Wiley & Sons,. [6] Hendy, D.C., and A.A. Duncan. "Aea Efficient DSP Datapath Synthesis." Design Automation Confeence (995): IJCA TM : 5