A Novel Parallel Deadlock Detection Algorithm and Architecture

Transcription

1 A Novel Paallel Deadlock Detection Aloithm and Achitectue Pun H. Shiu 2, Yudon Tan 2, Vincent J. Mooney III {ship, ydtan, codesin.ece.atech.eduedu,2 Hadwae/Softwae RTOS Goup Low Powe Compile Goup Assistant Pofesso,,2 Electical and Compute Enineein Adjunct Assistant Pofesso, Collee of Computin Geoia Institute of Technoloy Atlanta, GA USA ece.atech.eduedu Apil, 2 CODES 2

2 Oveall Outline Motivation - Technoloy Tends Backound - Deadlock Detection Paallel Aloithm Paallel Achitectue Expeimental Results Conclusion Apil, 2 CODES 2

3 Motivation - Technoloy Tends Many of today s chip desins contain 2 pocessos, e.., a DSP and a micocontolle Futue SoC desins ae likely to include 4-44 heteoeneous pocessos -5 on-chip hadwae esouces FFT, Vitebi filte, wieless communication Multitheaded softwae which dynamically equests and uses the esouces Apil, 2 CODES 2

4 SoC Softwae Ideally, poammes of such futue SoC desins would only wite deadlock-fee code If not, we povide a way to detect deadlock vey fast Use can wite code to ecove fom deadlock Apil, 2 CODES 2

5 Deadlock Detection Unit (DDU) Small & scalable paallel hadwae unit Multiple equestos & esouces In this pape, the only equestos ae pocessos and the only esouces ae specialized hadwae units like FFT Apil, 2 CODES 2

6 Oveall Outline Motivation - Technoloy Tends Backound - Deadlock Detection Paallel Aloithm Paallel Achitectue Expeimental Results Conclusion Apil, 2 CODES 2

7 Backound: Deadlock Condition P Q2 Popeties of Resouces Q P2 Mutual Exclusion: Any A esouce can be held exclusively, makin it unavailable to othe pocessos Non-peemption: Any A esouces can be eleased only by the pocessos holdin the esouce. Non Behavio of pocessos Patial Allocation: a pocesso may hold some esouces while the pocesso equests additional esouces. Blocked Wait: pocesso must wait fo unavailable esouces to become available. Apil, 2 CODES 2

8 Pevious Aloithms Run Time Geneally the un time is O(m*n), whee m is the numbe of pocessos and n is the numbe of esouces. Path Based, O(e), o O(e m*n), whee e is the set of edes. Tee Based, O(m*n) Matix Based, O(m*n) Messae Passin Based, O(m*n) Apil, 2 CODES 2

9 Oveall Outline Motivation - Technoloy Tends Backound - Deadlock Detection Paallel Aloithm Paallel Achitectue Expeimental Results Conclusion Apil, 2 CODES 2

10 Example pocesso pocesso equest ant esouce esouce equest ant Apil, 2 CODES 2

11 Example Souce node Sink ede Link nodes Simple path Sink node Link ede Simple path Souce ede Apil, 2 CODES 2

12 Matix Repesentation Each ow coesponds to a equesto (pocesso) p i epesents equesto (pocesso) i Each column coesponds to a esouce q j epesents esouce j Enties in the matix (( ij ) epesents a equest (( ij ) epesents a ant epesents no action (neithe equest no ant) Apil, 2 CODES 2

13 Popeties Poposed Aloithm Matix Based Modified Reduction Technique Handlin multiple equests, and ants at the same time. Requies simple bit-wise boolean opeations. Apil, 2 CODES 2

14 SoC Example P\Q q(icp IcP) q2(pci) q3(wi) p(dsp) p2(vsp) Apil, 2 CODES 2

15 Deadlock and Cycle Relation Deadlock cycles Cycles Deadlock (As shown in the ed) DSP VSP IcP PCI WI P\Q q(icp IcP) q2(pci) q3(wi) p(dsp) p2(vsp) Apil, 2 CODES 2

16 Apil, 2 CODES 2 [ ] [ ] c c c M M [ ] [ ] c c c M M Matix Repesentation [ ] [ ] c c c M M M

17 Apil, 2 CODES 2 iht bo XOR M M iht bo XOR M M Matix Repesentation: calculation of M bo and XOR iht

18 Matix Repesentation: calculation of M cbo and XOR below XOR M M below c cbo [ ] [ ] [ ] Apil, 2 CODES 2

19 Result of fist iteation XOR XOR below iht [ ] Based on esult, we set all enties in column 3 to zeo: M Apil, 2 CODES 2

20 Multiple Iteations Continuin in this way, we continue iteatin until no moe chanes When finished, if M is all zeos, we have no deadlock; othewise, we do have deadlock This aloithm equies at most 2*min(m,n) iteations 2*min(m,n) iteations Apil, 2 CODES 2

21 Oveall Outline Motivation - Technoloy Tends Backound - Deadlock Detection Paallel Aloithm Paallel Achitectue Expeimental Results Conclusion Apil, 2 CODES 2

22 3 Pocessos/3 Resouces: Achitectue Apil, 2 CODES 2

23 Oveall Outline Motivation - Technoloy Tends Backound - Deadlock Detection Paallel Aloithm Paallel Achitectue Expeimental Results Conclusion Apil, 2 CODES 2

24 Expeiments Assumption Softwae Cycle: 83.3 MHz pocesso Hadwae Cycle: Synthesized fom ate-level desciption Clock as fast as citical path (e.., 4.2 ns 242 MHz Clock) Clock same as CPU clock 83.3 MHz clock (2 ns cycle time) Simulation Pevious Aloithm: PowePC 75 uns.c in Seamless CVE Poposed Aloithm: Synopsys VCS uns.v ~ times faste 99% un time eduction Apil, 2 CODES 2

25 Apil, 2 CODES 2 Aea and Delays of DDU x5 5x x x x7 7x x5 5x x3 2x3 Wost Wost Case Case Custom Custom Clk Clk (ns) (ns) Wost Wost Case Case (# steps) (# steps) Delay/ Delay/ Step Step (ns) (ns) Aea Aea AMI AMI.3u.3u Lines Lines of of Veilo Veilo P P Times Times Q Q 6ns 6ns 2ns 2ns 84ns 84ns 6ns 6ns 24ns 24ns Wost Wost Case Case 83.3Mhz 83.3Mhz (ns) (ns)

26 Hadwae vs. Softwae Pefomance Numbe of Cycles Numbe of Edes Apil, 2 CODES 2

27 Example: Lookup Sevice Apil, 2 CODES 2

28 Example SoC Achitectue Apil, 2 CODES 2

29 Event Sequence of the Example Time t t2 t3 t4 t5 Event No. e e2 e3 e4 e5 Events MPC75- equests FFT, MPEG ae anted to MPC75- immediately MPC equests FFT, PCI; PCI is anted to MPC immediately. MPC equests FFT, MPEG. FFT is eleased by MPC75- FFT is anted to MPC75-2. Apil, 2 CODES 2

30 Adjacency Matices Apil, 2 CODES 2

31 Sequence of Events Apil, 2 CODES 2

32 Deadlock Detection Time and Total Execution Time Method of Deadlock Detection Detection Time (cycles) t 5 + Softwae 6,38 23,26 DDU 2 7,225 23,26-7,225 23,26 Soveall 68.9% Apil, 2 CODES 2

33 Conclusion Deadlock Detection Unit vey small aea, even fo 5x5 O sw (m*n) to O hw (min(m,n)) speedup Linealy scalability in min(m,n) Handle simultaneous equests/ants DDU can be used by multipocesso SoC sofwae code to detect deadlock quickly and then, fo example, elease esouces to et out of deadlock Apil, 2 CODES 2

34 Futue Wok Inteate DDU into an RTOS Monito DDU output DDU API Extend to handle multiple blocked wait theads on one CPU: RTOS on each pocesso aeates equests which have the blocked wait popety each aeate oup is epesented by a unique pocesso ow Ty diffeent ecovey schemes Pehaps some hadwae assist in ecovey Apil, 2 CODES 2