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2 9 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems Edal Ouklu, Jafa Saniie and Xin Xiao Illinois Institute of Technology USA Intoduction Discete Fouie Tansfom (DFT) is one of the coe opeations in digital signal pocessing and communication systems Many fundamental algoithms can be ealized by DFT, such as convolution, spectum estimation, and coelation Futhemoe, DFT is widely used in standad embedded system applications such as wieless communication potocols equiing Othogonal Fequency Division Multiplexing (Wey et al, 007), and ada image pocessing using Synthetic Apetue Rada (Fanucci et al, 999) In pactice, DFT is difficult to implement diectly due to its computational complexity To educe the degee of computation, Cooley and Tukey poposed the well-known Fast Fouie Tansfom (FFT) algoithm, which educes the calculation of N-point DFT fom O(N ) to O(N/log N) (Poakis & Manolakis, 006) Nevetheless, fo embedded systems, in paticula potable devices; efficient hadwae ealization of FFT with small aea, low-powe dissipation and eal-time computation is a significant challenge The challenge is even moe ponounced when FFTs with lage tansfom lengths (>0 points) need to be ealized in embedded hadwae Theefoe, the objective of this eseach is to investigate hadwae efficient FFT achitectues, emphasizing compact, low-powe embedded ealizations As VLSI technology evolves, diffeent achitectues have been poposed fo impoving the pefomance and efficiency of the FFT hadwae Pipelined achitectues ae widely used in FFT ealization (Li & Wanhamma, 999; He & Tokelson, 996; Hopkinson & Butle, 99; Yang et al, 006) due to thei speed advantages Highe adix (Hopkinson & Butle, 99; Yang et al, 006) and multi-buttefly (Bouguezel et al, 00; X Li et al, 007) stuctues can also impove the pefomance of the FFT pocesso significantly, but these stuctues equie substantially moe hadwae esouces Altenatively, shaed memoy based schemes with a single buttefly calculation unit (Cohen, 976; Ma, 99, 999; Ma & Wanhamma, 000; Wang et al, 007) ae pefeed in many embedded FFT pocessos since they equie least amount of hadwae esouces Futhemoe, in-place ing stategy is a pactical choice to minimize the amount of data memoy With in-place stategy, the two outputs of the buttefly unit can be witten back to the same memoy locations of the two inputs, and eplace the old data Fo in-place FFT pocessing, two data ead and two data wite opeations occu at evey clock cycle Multiple memoy banks and conflict-fee ing logic ae equied to ealize fou data accesses in one clock cycle Consequently, a typical FFT pocesso is composed of thee majo components: i) buttefly calculation units, ii) conflict fee geneatos fo both data and coefficient accesses and iii) multi-bank memoy units wwwintechopencom

3 8 Fouie Tansfoms - Appoach to Scientific Pinciples In this study, seveal techniques ae developed fo educing the hadwae logic and powe equiements fo these thee components: In ode to optimize the conflict fee ing logic, a modified buttefly stuctue with input/output exchange cicuits is pesented in Section CORDIC based FFT algoithms ae pesented fo multiplie-less and coefficient memoy-less implementation of the buttefly unit in Section Memoy bank patitioning and bitline segmentation techniques ae pesented fo dynamic powe eduction of data memoy accesses Futhemoe, a special coefficient memoy ing logic which educes the switching activity is poposed in Section Case studies with ASIC and FPGA synthesis esults demonstate the pefomance gains and feasibility of these FFT implementations on embedded systems Hadwae efficient ealization of fast Fouie tansfom Thee is an ongoing inteest in hadwae efficient FFT achitectues Cohen (Cohen, 976) intoduced a simplified contol logic fo FFT geneation, which is composed of paity checks, bael shiftes and countes based on the fact that two data es of evey buttefly opeations diffe in thei paity Ma (Ma, 999) poposed a method to ealize the adix- ing logic which educes the geneation delay by avoiding paity check (XOR opeations), but bael shiftes ae still needed Futhemoe, Ma s appoach is not in-place, so moe egistes and elated contol logic ae needed to buffe the inteim data to avoid the memoy conflict Yang (Yang et al, 006) poposed a locally pipelined adix-6 FFT ealized by two adix- deep feedback (RSD F) butteflies This achitectue can impove the thoughput of the FFT pocessing and educe the complex multiplies and addes compaed to othe pipelined methods, but it needs exta memoy and thee is significantly moe coefficient access due to adix-6 implementation Li (X Li et al, 007) poposed a mixed adix FFT achitectue, which contains one adix- buttefly and one adix- buttefly The two butteflies shae the multiplies, which educe the hadwae consumption, but the geneation is based on XOR logic, and simila to Cohen's design Next section descibes in detail ing schemes that emphasize educed hadwae Conflict-fee ing fo FFT The N-point discete Fouie tansfom is defined by N π j nk nk nk N N N n= 0 Xk ( ) = xnw ( ) k= 0,,, N, W = e () Fig shows the signal flow gaph of 6-point decimation-in-fequency (DIF) adix- FFT (Poakis & Manolakis, 006) FFT algoithm is composed of buttefly calculation units: x ( ) ( ) ( ) m+ p = xm p + xm q () ( ) [ ( ) ( )] xm+ q = xm p xm q WN () Equations (), () descibe the adix- buttefly calculation at Stage m as shown in Fig Paallel and in-place buttefly opeation using two memoy banks of two-pot memoy wwwintechopencom

4 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 8 units equies that the two inputs of any buttefly ae ead fom diffeent banks of memoy and the two outputs ae witten to the same locations as the inputs As shown in Fig, in the conventional FFT ing scheme, only the butteflies in the fist stage satisfy this equiement Two inputs and two outputs of buttefly opeations in all othe stages ae oiginating fom and sinking to the same memoy bank Theefoe, a special ing scheme is equied to pevent the conflicting es Cohen (Cohen, 976) used paity check to sepaate the data into two memoy banks Fig is the signal flow gaph of Cohen s appoach and it shows that inputs and outputs of any buttefly stage utilize sepaate memoy banks The es of buttefly opeations ae inplace located The dawback of Cohen s method is the geneation delay In ode to educe the delay of the geneation, Ma (Ma, 999) poposed an altenative ing scheme which avoids using paity check The signal flow gaph of Ma s scheme is shown in Fig In Ma s scheme, two inputs of a buttefly unit oiginate fom two sepaate memoy banks but two outputs of the buttefly unit utilize the same memoy bank The inputs and outputs of a buttefly unit ae not in-place Theefoe, exta egistes and elated contol logic ae needed to buffe the outputs of the buttefly until next buttefly calculation is finished in ode to ealize the in place opeation Compaed to Cohen s appoach which uses both paity check and bael shiftes, Ma s method needs only bael shiftes and avoids paity check, esulting in a educed geneation delay Howeve, Ma s appoach consumes moe hadwae esouces to ealize the in-place opeation In the following section, a hadwae efficient FFT engine with educed citical path delay is poposed Addessing logic is educed by using a buttefly stuctue which modifies the conventional one by adding exchange cicuits at the input and output of the buttefly (Xiao, et al, 008] With this buttefly stuctue, the two inputs and two outputs of any buttefly can be exchanged; hence all data es in FFT pocessing can be eodeed Using this flexible input and output odeing, ing logic is designed to be in-place and it does not need bael shiftes Memoy Bank0 Memoy Bank Input x(n) Output X(k) Stage 0 Stage Stage Stage W0 W W W W W5 W6 W7 W0 W W W6 W0 W W W6 W0 W W0 W W0 W W0 W Fig Signal flow gaph of 6-point FFT wwwintechopencom

5 8 Fouie Tansfoms - Appoach to Scientific Pinciples x m (p) x m+ ( p) x m (q) W N x ( q m+ ) Fig Buttefly unit at stage m Memoy Bank0 (Paity even) Memoy Bank (Paity odd) Input x(n) Output X(k) 0 Stage 0 Stage Stage Stage Fig Signal flow gaph of 6-point FFT using Cohen s method (Cohen, 976) Memoy Bank0 Input x(n) Output X(k) 0 Stage 0 Stage Stage Stage Memoy 0 Bank 5 Fig Signal flow gaph of 6-point FFT using Ma s method (Ma, 999) wwwintechopencom

6 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 85 Reduced geneation logic with the modified buttefly FFT (mbfft) This ing scheme is based on a modified buttefly FFT (mbfft) stuctue, which is shown in Fig 5 The main diffeence between the modified buttefly stuctue and the conventional one is the addition of two exchange cicuits that ae placed at both the input and the output of the buttefly unit Each exchange cicuit is composed of two (:) multiplexes; when the exchange contol signal C o C is, the data will be exchanged, othewise they keep thei locations y m (p) :MUX 0 x m (p) x m+ ( p) :MUX 0 y m+ ( p) y m (q) :MUX 0 x m (q) W N x m+ ( q) :MUX 0 y m+ ( q) C Fig 5 Modified buttefly stuctue Equation () shows the function: C If C=: Else: If C=: y x ( p) = y ( q), x ( q) y ( p); m m m = x ( p) = y ( p), x ( q) y ( q); m m m = ( p) = xm+ ( q), ym+ ( q) xm ( p); m + = + m m else: y ( p) = xm+ ( p), ym+ ( q) xm ( q); m + = + Based on this buttefly stuctue, all data within the FFT pocessing can be eodeed by setting the diffeent values of the exchange contol signals C and C The contol signals ae chosen such that the input data always oiginate fom two sepaate memoy banks and output data ae witten to the same memoy location in ode to achieve in-place opeation 6-point mbfft implementation Fo 6-point mbfft, the signal flow gaph is shown in Fig 6 In the figue, the buttefly inputs o outputs indicated by boken lines denote that the data have been exchanged Fig 7 shows the complete geneation achitectue and components fo 6-point FFT implementation The geneation logic is composed of a 5-bit counte D, thee () wwwintechopencom

7 86 Fouie Tansfoms - Appoach to Scientific Pinciples invetes, a -bit shifte, thee (:) multiplexes, two (:) multiplexes, fou multi-bit (:) multiplexes and delay elements Stage Counte S indicates which stage of FFT is cuently in pogess and contols the two (:) multiplexes to geneate the coect exchange contol signals C and C fo the buttefly opeation The -bit shifte shifts one bit at each stage and it contols thee (:) multiplexes to geneate the coect M Since this technique is in-place, the es fo ead and wite ae same with the exception of a delay intoduced fo compensating the buttefly computation time Table I pesents the counte values (contol logic) which ae used to geneate the es fo M0 and M memoy banks Memoy Bank0 Memoy Bank Input x(n) Output X(k) 0 Stage 0 Stage Stage Stage Fig 6 Signal flow gaph of 6-point mbfft Counte Bbbb ( ) 0 Counte Bb ( bb 0) Stage 0 (exchange contol signal: C=0,C=b ) Bank0 Bank bbb bbb 0 0 Stage (exchange contol signal: C= b,c= b ) Stage (exchange contol signal: C= b,c= b 0 ) Bank0 Bank Bank0 Bank bbb 0 bbb 0 bbb 0 bbb 0 Stage (exchange contol signal: C= b 0,C=0) Bank0 Bank bbb 0 bbb Table Addess geneation table fo the 6-point mbfft wwwintechopencom

8 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 87 x m+ ( ) x m+ ( q) p :MUX 0 y m+ ( ) y m+ ( q) Buttefly Data Out Read Addess y m (p) y m (q) x m (p) x m (q) :MUX 0 :MUX 0 :MUX 0 p Data In Memoy Bank M0 Wite Addess Data In Memoy Bank Data Out M Wite Addess Read Addess Delay Delay Delay :MUX 0 :MUX 0 :MUX 0 C :MUX C :MUX Delay Delay Delay -bit Shifte D D D -bit Invete b b b0 b b Stage Counte S Counte D b b b 0 Buttefly Counte B Fig 7 Addess geneation cicuits fo 6-point mbfft N-point mbfft implementation In ode to genealize the ing scheme fo N = n - point FFT, the necessay cicuit components of the ing and contol logic can be listed as follows: (n-)-bit Buttefly Counte B= bn bn bb0, (n-) invetes which geneate the complement of the Buttefly Counte B= bn bn bb0 fom counte B, log n - bit Stage Counte S = ( n ),,,,0 Two memoy banks, Bank 0 (M0) and Bank (M) In pactice, Stage Counte S and Buttefly Counte B can be combined to a single counte D, whee B is the least significant (n-) bits of counte D, and S is the most significant log n bits of counte D At any time, the ead and wite es of M0 is exactly same as the value of Buttefly Counte B Fo M, the ead and wite at Stage s is bn bn bn s bn s bb0, which is a combination of countes B and B The exchange contol signal C is equal to bn s (assume bn 0 ), and C is equal to bn s (assume b 0 ) The of twiddle factos at stage s is given by bn s bn s b000 ( s 0 s) wwwintechopencom

9 88 Fouie Tansfoms - Appoach to Scientific Pinciples VLSI synthesis esults The mbfft achitectue is synthesized using TSMC CMOS 08µm technology Synthesis is pefomed with Cadence Build Gates and Encounte tools The synthesis esults fo 6-point FFT with -bit complex numbe input show a maximum clock fequency of 80MHz with 0665mm aea and 065mW total powe consumption fo the complete FFT opeation including buttefly unit, geneation unit, and memoy cicuits In ode to compae diffeent FFT ing methods, the logic complexity can be evaluated simila to (Ma, 999), based on gate counts The sizes of some basic cicuits and gates ae listed in Table Estimated gate count compaison fo 0-point FFT of -bit complex data (6-bit each fo the eal pat and imaginay pat) is shown in the Table In tems of aea, mbfft scheme equies % fewe numbe of tansistos This eduction is mainly due to the diffeence in logic complexity of the multiplexes and bael shiftes Based on the gate counts in Table (and confimed by synthesis esults), -input (:) multiplexe is appoximately times smalle than (-) bael shifte in tems of aea The delay of geneation fo both ead and wite opeations in the mbfft ing scheme is detemined by two stages of multiplexes, whee the fist stage uses an -input (:) multiplexe and the second stage uses a -input (:) multiplexe fo a -point FFT opeation (see Fig 7) In (Ma, 999), wost-case geneation delay is dominated by an (-)-bit bael shifte and a (:)-multiplexe An (-)-bit bael shifte equies log ( ) stages of (:) multiplexes in the citical path Cohen s geneation method (Cohen, 976) uses an -bit paity check unit, an (-)-bit bael shifte, and two (:) multiplexes in the citical path Standad cell synthesis esults in Table show that the poposed mbfft geneation scheme is faste compaed to (Cohen, 976) and (Ma, 999) fo lage FFTs, due to the complex wiing and paasitic capacitances in bael shiftes and elimination of the paity-check opeation Compaed to a pipelined FFT achitectue such as RSD F given in (Yang et al, 006), the shaed memoy achitectues such as mbfft offe significantly educed hadwae cost and powe consumption at the expense of (slowe) thoughput RSD F equies log N- multiplies, log N addes and 0log N multiplexes fo the buttefly opeations in an N- point FFT In contast, only one multiplie, two addes and fou multiplexes ae used in the mbfft achitectue datapath The latency (total clock cycles) of a pipelined FFT achitectue is faste by a facto of log Howeve, the maximum achievable clock fequency would N be less than the mbfft design due the inceased complexity of the RSD F datapath and geneation Hence, fo embedded applications, the poposed educed logic, shaed memoy FFT appoach with modified buttefly units pesents a moe viable solution Types of Gates and Cicuits No of Tansistos -Input XOR 0 - Multiplexe 6 0- Multiplexe -bit Registe/Latch 0 9-bit Counte 8 -bit Counte 70 9-bit Bael Shifte 5 0-bit Bael Shifte 68 Table Tansisto counts fo CMOS cells (Ma, 999) wwwintechopencom

10 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 89 Design Schemes Poposed mbfft Design (Ma, 999) (Cohen, 976) Components Quantity Type -bit Counte 9 Invetes 9-bit Shifte 9 -bit : Multiplexe -bit 0: Multiplexe -bit : Multiplexe 9-bit Latches -bit Counte 9-bit Bael Shiftes 9-bit Latches -bit Latches 9-bit : Multiplexes -bit : Multiplexes -bit Counte 9-bit Counte 9-bit Latch 0-bit Bael Shifte 9-bit : Multiplexe -bit :Multiplexe 9-bit Addess Paity Geneato Tansisto Counts Table Addess geneation logic compaison fo 0-point FFT with -bit complex data FFT size = n Poposed mbfft (Ma, 999) (Cohen,976) n= 8 ns 8 ns 8 ns n=8 0 ns 5 ns 50 ns n=0 7 ns 7 ns 6 ns n=6 59 ns 85 ns 87 ns Table Delay compaison of geneation cicuits Multiplieless FFT achitectues using CORDIC algoithm In FFT pocessos, buttefly opeation is the most computationally demanding stage Taditionally, a buttefly unit is composed of complex addes and multiplies A complex multiplie can be vey lage and it is usually the speed bottleneck in the pipeline of the FFT pocesso The Coodinate Rotation Digital Compute (CORDIC) (Volde, 959) algoithm is an altenative method to ealize the buttefly opeation without using any dedicated multiplie hadwae CORDIC algoithm is vesatile and hadwae efficient since it equies only add and shift opeations, making it suitable fo the buttefly opeations in FFT (Despain, 97) Instead of stoing actual twiddle factos in a ROM, the CORDIC-based FFT pocesso needs to stoe only the twiddle facto angles in a ROM fo the buttefly opeation In ecent yeas, seveal CORDIC-based FFT designs have been poposed fo diffeent applications (Abdullah et al, 009; Lin & Wu, 005; Jiang, 007; Gaido & Gajal, 007) In (Abdullah et al, 009), non-ecusive CORDIC-based FFT was poposed by eplacing the wwwintechopencom

11 90 Fouie Tansfoms - Appoach to Scientific Pinciples twiddle factos in FFT achitectue by non-iteative CORDIC mico-otations It educes the ROM size, howeve, it does not eliminate it completely (Lin & Wu, 005) poposed a mixed-scaling-otation CORDIC algoithm to educe the total iteations, but it inceases the hadwae complexity (Jiang, 007) intoduced Distibuted Aithmetic (DA) to the CORDIC-based FFT algoithms, but the DA look-up tables ae costly in implementation (Gaido & Gajal, 007) poposed a memoy-less CORDIC algoithm to educe the memoy equiements fo a CORDIC-based FFT pocesso by using only shift opeations fo multiplication Conventionally, a CORDIC-based FFT pocesso needs a dedicated memoy bank to stoe the necessay twiddle facto angles fo the otation In ou ealie wok (Xiao et al, 00), a modified CORDIC algoithm fo FFT pocessos is poposed which eliminates the need fo stoing the twiddle facto angles The algoithm geneates the twiddle facto angles successively by an accumulato With this appoach, memoy equiements of an FFT pocesso can be educed by moe than 0% Memoy eduction impoves with the inceasing adix size Futhemoe, the angle geneation cicuit consumes less powe consumption than angle memoy accesses Hence, the dynamic powe consumption of the FFT pocesso can be educed by as much as 5% Since the citical path is not modified with the CORDIC angle calculation, system thoughput does not change In the following sections, CORDIC algoithm fundamentals and the design of the poposed memoy efficient CORDIC-based FFT pocesso ae descibed CORDIC algoithm CORDIC algoithm was poposed by JE Volde (Volde, 959) It is an iteative algoithm to calculate the otation of a vecto by using only additions and shifts Fig 8 shows an example fo otation of a vecto V i y V ( xi+, y ) i+ i+ V i ( i i x, y ) φ α x Fig 8 Rotate vecto Vi( xi, y i) to Vi+ ( xi+, yi+ ) The following equations illustate the steps fo calculating the otation: xi+ = cos( α + φ) = ( cosαcosφ sinαsinφ) = x cosφ y sinφ i yi+ = sin( α + φ) = (sinαcosφ + cosαsin φ) = y cosφ + x sinφ i i i (5) (6) wwwintechopencom

12 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 9 If each otate angle φ is equal to actan i, then: x cos φ( x y i + = ) (7) i i i y cos ( i i+ = φ yi + xi ) (8) Since φ = actan i, cosφ can be simplified to a constant with fixed numbe of iteations: x ( i i+ = Ki xi yi di ) (9) y ( i i+ = Ki yi + xi di ) (0) i whee K i = cos(actan( )) and d i = ± Poduct of K i 's can be epesented by the K facto which can be applied as a single constant multiplication eithe at the beginning o end of the iteations Then, (9) and (0) can be simplified to: x i i+ = xi yi di (0) y + = y + x d () i i i i i The diection of each otation is defined by d i and the sequence of all d i 's detemines the final vecto d i is given as: d i if zi < 0 = + if zi 0 whee z i is called angle accumulato and given by () z ( actan i i+ = zi di ) () All opeations descibed though equations (0)-() can be ealized with only additions and shifts; theefoe, CORDIC algoithm does not equie dedicated multiplies CORDIC algoithm is often ealized by pipeline stuctues, leading to high pocessing speed Fig 9 shows the basic stuctue of a pipelined CORDIC unit π j nk N nk nk As shown in equation (), the key opeation of FFT is xn ( ) W N, ( WN = e ) This is π equivalent to "Rotate xn ( ) by angle nk " opeation which can be ealized easily by the N CORDIC algoithm Without any complex multiplications, CORDIC-based buttefly can be fast An FFT pocesso needs to stoe the twiddle factos in memoy CORDIC-based FFT doesn t have twiddle factos but needs a memoy bank to stoe the otation angles Fo mn N adix-, N-point, m-bit FFT, bits memoy needed to stoe angles In the next section, a new CORDIC based FFT design which does not equie any twiddle facto o angle memoy units is pesented This design uses a single accumulato fo geneating all the necessay angles instantly and does not have any pecision loss wwwintechopencom

13 9 Fouie Tansfoms - Appoach to Scientific Pinciples Reduced memoy CORDIC based FFT Although seveal multi-bank ing schemes have been used to ealize paallel and pipelined FFT pocessing (Ma, 999; Xiao et al, 008), these methods ae not suitable fo the educed memoy CORDIC FFT In these schemes, the twiddle facto angles ae not in egula inceasing ode (see Table 5), esulting in a moe complex design fo angle geneatos As shown in Table 6, using a special ing scheme fist poposed in (Xiao et al, 009), the twiddle facto angles follow a egula, inceasing ode, which can be x0 y0 z0 Registe Registe Registe φ 0 >>0 >>0 +/- +/- +/- Registe Registe Registe φ >> >> +/- +/- +/- Registe Registe Registe φ n >>n >>n +/- +/- +/- xn yn zn Fig 9 Basic stuctue of a pipelined CORDIC unit geneated by a simple accumulato Table 6 shows the geneation table of the 6- point adix- FFT It can be seen that twiddle facto angles ae sequentially inceasing, and evey angle is a multiple of the basic angle π, which is π fo 6-point FFT Fo N 8 diffeent FFT stages, the angles incease always one step pe clock cycle Hence, an angle wwwintechopencom

14 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 9 geneato cicuit composed of an accumulato, and an output latch can ealize this function, as shown in Fig 0 Contol signal fo the latch that enables o disables the accumulato output is simple and it is based on the cuent FFT buttefly stage and RAM bits b b b 0 (see Table 6) π N Registe Latch Angle CLK Fig 0 Angle geneato fo the CORDIC based FFT Accumulato Contol Buttefly Counte B(bbb0) RAM b0bb Stage 0 Stage Stage Stage Twiddle facto angle RAM bb0b Twiddle facto angle RAM bbb0 Twiddle facto angle RAM b0bb Twiddle facto angle π 8 00 π 8 00 π π π 8 0 π 8 0 π π 8 00 π π 8 0 6π 8 0 π π 8 0 π π 8 6π 8 π 8 0 Table 5 Addess geneation table of Ma s (Ma, 999) design fo 6-point adix- FFT Fig shows the achitectue of the poposed no-twiddle-facto-memoy design fo adix- FFT Fou egistes and eight -to- multiplexes ae used Registes ae needed befoe and afte the buttefly unit to buffe the intemediate data in ode to goup two sequential buttefly opeations togethe Theefoe, the conflict-fee in-place data accessing can be ealized This egiste-buffe design can be extended to any adix FFTs Fo adix-, the wwwintechopencom

15 9 Fouie Tansfoms - Appoach to Scientific Pinciples stuctue can be simplified by using just egistes, but fo adix- FFT, needed Fig shows the stuctue fo adix- FFT egistes ae Buttefly Counte B(bbb0) RAM bbb0 Stage 0 Stage Stage Stage Twiddle facto angle RAM b0bb Twiddle facto angle RAM bb0b Twiddle facto angle RAM bbb0 Twiddle facto angle π π 8 00 π π 8 0 π π 8 00 π 8 00 π π 8 0 π 8 0 π π 8 0 6π 8 0 π π 8 6π 8 π 8 0 Table 6 Addess geneation table fo 6-point adix- FFT with the poposed angle geneato Data Data In Out RAM Registe Buttefly Registe Data Data In Out RAM Registe Angle Geneato Registe Fig Radix- FFT pocesso with no-twiddle-facto-memoy wwwintechopencom

16 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 95 Data Data In Out RAM R R R R Data Data In Out RAM Data Data In Out RAM R R R Radix Buttefly Angle Geneato R R R Fig Poposed adix- CORDIC-based FFT Fo an N = n -point FFT, the ing and contol logic ae composed of seveal components: An ( n ) -bit buttefly counte B= bn bn bb0 will povide the sequences and the contol logic of the angle geneato In stage S, the memoy is given byb s bs bbbn bn b, which is otate ight S bits of buttefly counte B 0 s Meanwhile, the contol logic of the latch of the angle geneato is detemined by the sequence of the patten; bn bn bs00 ( S 0 s) Fo adix-, N = n -point, m-bit FFT, (each data is m-bit complex numbe; m-bit each fo the eal pat and imaginay pat) by using the poposed angle geneato, 5 mn bits memoy equied by the conventional CORDIC can be educed to mn which coesponds to 0% eduction Fo highe adix FFT, the eduction is even moe significant Fo adix- FFT, the saving is ( ) mn ( ) mn bits out of, which conveges to % eduction Due to finite wodlength, as the accumulato opeates, the pecision loss will accumulate as well In ode to this issue, moe bits (wide wodlength) can be used fo the fundamental angle π/n and the accumulato logic Fo example, fo 0-point FFT, the accumulato is extended fom 6 bits to bits and no pecision loss is obseved compaed to a conventional angle-stoed CORDIC FFT pocesso FPGA synthesis esults The poposed educed memoy CORDIC based FFT designs fo both adix- and adix- FFT algoithms have been ealized by Veilog-HDL and implemented on an FPGA chip (STRATIX-III EPSE50C) Synthesis esults shown in Table 7 show that these designs can educe memoy usage fo FFT pocessos without any tangible incease in the numbe of logic elements used when compaed against the conventional CORDIC implementation (ie, wwwintechopencom

17 96 Fouie Tansfoms - Appoach to Scientific Pinciples angles ae stoed in memoy) Futhemoe, dynamic powe consumption is educed (up to 5%) with no delay penalties The synthesis esults match with the theoetical analysis Radix- Radix- 56-point FFT Total logic elements Poposed CORDIC FFT (angle geneato),7 (9-bit accum) Conventional CORDIC FFT (angles stoed),86 Poposed CORDIC FFT (angle geneato) 5,89 (0-bit accum) Conventional CORDIC FFT (angles stoed) 5,76 Total memoy 8,67 0,70 8,78,800 Dynamic Powe 687 mw 56mW 75 mw 9506 mw 0-point FFT Total logic elements,77 (-bit accum),78 5,99 (-bit accum) 5,797 Total memoy,8,0,0 5,59 Dynamic Powe 507 mw 7598 mw 90 mw 966 mw 096-point FFT Total logic elements Total memoy bits,809 (-bit accum),757 5,99 (-bit accum) 5,86,55 6,0,608 80,760 Dynamic Powe 78 mw 85 mw 50 mw 577 mw Table 7 FPGA implementation esults fo Radix- and Radix- FFT Low-powe FFT ing schemes Fo embedded applications, powe dissipation is often a cucial design goal (Ma & Wanhamma, 999) poposed a new ing logic to impove the memoy accessing speed and to educe the powe consumption (Hasan et al, 00) designed a new coefficient odeing method to educe the powe consumption of adix- shot-length FFTs Gate-level algoithms have also been poposed (Zainal at al, 009; Saponaa, 00) to educe the FFT pocesso s powe consumption by lowe supply voltage techniques and/o voltage scaling Powe consumption of FFT pocessos can be significantly educed by optimizing both data and coefficient memoy accesses Dynamic powe consumption in CMOS cicuits can be chaacteized by the following equation: P = α C V f () dynamic total DD whee α is the switching activity, V DD is the supply voltage, f is the fequency and C total is the total switching capacitance chaging and dischaging in the cicuit In paticula, wwwintechopencom

18 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 97 achitectual techniques can educe two paametes in (), C total and These techniques ae discussed next: Fist, a multi-bank memoy stuctue is poposed fo data memoy accesses, esulting in educed oveall capacitance load on the SRAM bit-lines Second, a new buttefly calculation ode educes the memoy access fequency fo twiddle factos and minimizes the switching activity Memoy bank patitioning Since FFT opeation lagely consists of data and twiddle facto memoy accesses, it is desiable to educe the powe dissipation caused by memoy accesses Memoy bank patitioning and bitline segmentation is an impotant technique to educe the powe dissipation in SRAMs The bitlines (each ead and wite pot is associated with one bitline) in the SRAM logic ae a significant souce of enegy dissipation due to the lage capacitive load This capacitance has two components, wie capacitance of the bitlines and the diffusion capacitance of each pass tansisto connecting bitline to bitcells Hence, the capacitive load inceases linealy with the components attached to the bitline ie, the numbe of wods o size of the memoy In ode to educe this lage capacitive load, the data memoy can be patitioned into fou memoy banks instead of two As a esult, the capacitive loading in each memoy bank is loweed since the bitline wie length and the numbe of pass tansistos connected to the bitline is now only one fouth of the oiginal bitline The fist two memoy banks, bank0 and bank ae accessed by the uppe leg of the buttefly stuctue, and bank and bank ae accessed by the lowe leg of the buttefly (see Fig ) The most significant bit (MSB) of the es detemine which two memoy banks will be accessed; the emaining two memoy banks will be inactive Multi-bank memoy stuctue has been poposed befoe (Ma & Wanhamma, 000), but a majo advantage of the poposed ing scheme is that the memoy bank switching occus only once in the middle of a stage In the fist half of the stage, same two memoy banks ae used and in the second half of the stage, the othe two memoy banks ae accessed Thee is no pechaging and dischaging of bitlines in the inactive memoy banks Input x(n) Output X(k) 0 Stage 0 Stage Stage Stage 0 Memoy Bank0 6 Memoy Bank Memoy Bank Memoy Bank Fig Signal flow gaph of 6-point FFT using memoy patitioning wwwintechopencom

19 98 Fouie Tansfoms - Appoach to Scientific Pinciples Reodeing coefficient access sequence The mbfft achitectue (see Section ) can be used to geneate the ing scheme fo educing twiddle facto memoy accesses and switching activity powe The twiddle facto access sequence is optimized fo minimizing data bus changes Fo all buttefly stages, the twiddle facto es ae odeed in such a way that the twiddle factos at the same ae gouped togethe and accessed sequentially This way, the twiddle facto ROM is not accessed evey clock cycle Reodeing of the coefficient access sequences is shown in Table 8 and Table 9 Fo example, in stage in Table 9, only 8 accesses ae needed instead of 6, and in stage, only accesses instead of 8 and so on Counte Bbbb ( ) 0 Bank 0, bbb 0 Stage 0 Stage Twiddle facto bb 0 Bank, bbb 0 Bank 0, bbb 0 Twiddle Facto b 0 Bank, bbb Bank0, bbb 0 Stage Stage Twiddle Bank, Bank0, Twiddle facto facto bbb 00 0 bbb b Bank, bbb Table 8 Addess geneation table fo the 6-point, educed memoy access FFT wwwintechopencom

20 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 99 Stage 0 Stage Counte B ( bbbb 0 ) Bank 0, Twiddle facto Bank, Bank 0, Twiddle facto Addess Bank, b bbb0 b bb 0 b bbb 0 b bb 0 b b b b 0b Bank0, bbbb 0 Stage Stage Stage Twiddle Bank, Bank0, Bank, Bank0, facto b 00 bbbb 0 bbbb 0 Twiddle facto 000 bbbb 0 bbbb 0 Twiddle facto Addess 000 Bank, bbbb Table 9 Addess geneation table fo the -point, educed memoy access FFT wwwintechopencom

21 00 Fouie Tansfoms - Appoach to Scientific Pinciples Equations (5) and (6) show the twiddle facto memoy access fequency fo shaed memoy methods (Xiao et al, 008) and the poposed educed memoy access method fo N = n point FFT ( ) Conventional method: n ( N) N N ( ) + = log + (5) Reduced memoy access method: n i n + = = N (6) i= Table 0 shows the twiddle facto memoy access fequency fo diffeent FFT lengths As FFT length inceases, the powe saving also scales up Implementation To implement an N = n -point FFT with educed coefficient memoy accesses, an (n-)-bit Buttefly Counte B= bn bn bb0, and a log n -bit Stage Counte S = ( n ),,,,0 is needed In addition, one (n-)-bit bael shifte is used: Assume RR( xuxu xu xx0, v) indicates otate-ight counte xx u u xu xx 0 by v bit At stage s, the ead and wite es of the uppe legs of the buttefly is Au = RR( bn bb0, s) = an an aa0, and b decides if bank0 o bank will be accessed n 6- point FFT - point FFT 6- point FFT 8- point FFT 56- point FFT 5- point FFT 0- point FFT 08- point FFT 096- point FFT 89- point FFT Conventional FFT design Reduced memoy access FFT design Reduction % 0% 5% 6% 67% 7% 75% 78% 80% 8% Table 0 Reduction in twiddle facto memoy access fequency Fo example, fo the -point FFT shown in Table 9, at stage, the of the uppe legs of the buttefly is RR( bbb0,) = bb0b, and when b =0, memoy bank0 will be accessed, when b =, memoy bank will be accessed Fo the ead and wite es of the lowe legs of the buttefly, (n-) invetes ae needed The is given by an an an s an s aa0, and b decides if bank o bank will be accessed at stage 0 At stage 0, when bn = 0, bank will be accessed When bn =, bank will be accessed Fo othe stages bn = 0 means bank will be accessed, bn = means bank will be accessed The of twiddle factos is given by an s a000 (S 0 s) Fig shows the components of the geneation logic using mbfft and fou memoy banks wwwintechopencom

22 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 0 y m+ ( p) y ( q m+ ) :MUX 0 :MUX 0 x m+ ( ) x ( q m+ ) p y m+ ( p) DataIn W_en W_Addess Memoy Bank M0 DataOut R_en R_Addess DataIn W_en W_Addess Memoy Bank M DataOut R_en R_Addess DataIn W_enW_Addess Memoy Bank M DataOut R_en R_Addess DataIn W_enW_Addess Memoy Bank M DataOut R_en R_Addess Delay Buttefly Delay Delay Delay Delay x m (p) x m (q) y m (p) :MUX 0 :MUX 0 y m (q) Delay :MUX 0 :MUX 0 :MUX 0 C :MUX C :MUX :MUX 0 :MUX 0 -bit Shifte D D D b a a :MUX 0 a 0 a 0 :MUX 0 b b Stage Counte S Counte D b b b 0 Buttefly Counte B Fig Addess geneation cicuits fo low-powe 6-point FFT using mbfft and fou memoy banks Shaed memoy design (Xiao et al, 008) Powe optimized design Total powe Dynamic powe Static powe Total powe Dynamic powe Static powe 5 point FFT 65mw 0mw 5000mw 657mw 857mw 5000mw 0 point FFT 7579mw 6579mw 5000mw 67679mw 678mw 5000mw 08point FFT 809mw 909mw 5000mw 76mw mw 5000mw 096 point FFT 089mw 69mw 5000mw 995mw 89mw 5000mw 89 point FFT 595mw 5mw 5000mw 897mw 897mw 5000mw Table FPGA synthesis esults Reduction in dynamic powe wwwintechopencom

23 0 Fouie Tansfoms - Appoach to Scientific Pinciples FPGA synthesis esults The low-powe FFT algoithm is implemented on an FPGA chip (ALTERA STRATIX EPS5F780C5) with FFT length up to 89 points as shown in Table The synthesis esults demonstate that dynamic powe eduction gows with the tansfom size, making this achitectue ideal fo applications equiing long FFT opeations 5 Conclusion This study focused on hadwae efficient and low-powe ealization of FFT algoithms Recent novel techniques have been discussed and pesented to ealize conflict-fee memoy ing of FFT Poposed methods eode the data and coefficient sequences in ode to achieve significant logic eduction (% less tansistos) and delay impovements within FFT pocessos Multiplieless implementation of FFT is shown using a CORDIC algoithm that does not need any coefficient angle memoy, esulting in % memoy and 5% powe eduction Finally, optimization of FFT dynamic powe consumption is pesented though memoy patitioning and educing coefficient memoy access fequency (6% powe eduction fo 89 point-fft) 6 Refeences Abdullah, S S; Nam, H; McDemot, M & Abaham, J A (009) A High Thoughput FFT Pocesso with No Multiplies IEEE Intenational Confeence on Compute Design, pp 85-90, 009 Bouguezel, S; Ahmad, M O & Swamy, M N S (00) A New Radix-/8 FFT Algoithm fo Length-Q X m DFTs IEEE Tansactions on Cicuits and Systems I, vol 5, no 9, pp 7-7, Septembe 00 Cohen, D (976) Simplified Contol of FFT Hadwae IEEE Tansactions on Acoustics, Speech, Signal Pocessing, vol, pp , Decembe 976 Despain, A M (97) Fouie Tansfom Computes Using CORDIC Iteations IEEE Tansactions on Computes, vol c-, no0, pp 99-00, Octobe 97 Fanucci, L; Foliti, M & Gonchi, F (999) Single-Chip Mixed-Radix FFT Pocesso fo Real-Time On-Boad SAR Pocessing 6th IEEE Intenational Confeence on Electonics, Cicuits and Systems, ICECS '99, vol, pp 5-8, Septembe 999 Gaido, M & Gajal, J (007) Efficient Memoy-Less CORDIC fo FFT Computation IEEE Intenational Confeence on Acoustics, Speech and Signal Pocessing, vol, no, pp -6, Apil 007 Hasan, M; Aslan, T & Thompson, J S (00) A Novel Coefficient Odeing Based Low Powe Pipelined Radix- FFT Pocesso fo Wieless LAN Applications, IEEE Tansactions on Consume Electonics, vol 9, no, pp 8-, Febuay 00 He, S S & Tokelson, M (996) A New Appoach to Pipeline FFT Pocesso Poceedings of 0 th Intenational Paallel Pocessing Symposium, pp , Apil 996 Hopkinson, T M & Butle, G M (99) A Pipelined, High-Pecision FFT Achitectue Poceedings of the 5 th Midwest Symposium Cicuits and Systems, vol, pp 85-88, August 99 wwwintechopencom

24 Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems 0 Jiang, R M (007) An Aea-Efficient FFT Achitectue fo OFDM Digital Video Boadcasting IEEE Tansactions on Consume Electonics, vol 5, no, pp - 6, 007 Li, W D & Wanhamma, L (999) A Pipeline FFT Pocesso Poceedings of IEEE Wokshop on Signal Pocessing Systems, pp 65-66, Octobe 999 Li, X; Lai, Z & Cui, J (007) A Low Powe and Small Aea FFT Pocesso fo OFDM Demodulato IEEE Tansactions on Consume Electonics, vol 5, no, pp 7-77, May 007 Lin, C & Wu, A (005) Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) Algoithm and Achitectue fo High-Pefomance Vecto Rotational DSP Applications IEEE Tansactions on Cicuits and Systems I, vol 5, no, pp 85-96, 005 Ma, Y (99) A Fast Addess Geneation Scheme fo FFT Pocessos, Chinese Jounal Computes, vol 7, no 7, pp 505-5, July 99 Ma, Y (999) An Effective Memoy Addessing Scheme fo FFT Pocessos IEEE Tansactions on Signal Pocessing, vol 7, no, pp 907 9, Mach 999 Ma, Y & Wanhamma, L (999) A Coefficient Access Contol fo Low Powe FFT Pocessos IEEE nd Midwest Symposium on Cicuits and Systems, vol, pp 5-5, Aug 999 Ma, Y & Wanhamma, L (000) A Hadwae Efficient Contol of Memoy Addessing fo High-Pefomance FFT Pocessos IEEE Tansactions on Signal Pocessing, vol 8, no, pp 97-9, Mach 000 Poakis, J G; & Manolakis, D G (006) Digital Signal Pocessing Pinciples, Algoithms, and Applications, Pentice Hall, ISBN Saponaa, S; Seafini, L & Fanucci, L (00) Low-Powe FFT/IFFT VLSI Maco Cell fo Scalable Boadband VDSL Modem The d IEEE Intenational Wokshop on Systemon-Chip fo Real-Time Applications, pp6-66, June 00 Volde, J (959) The CORDIC Tigonometic Computing Technique IEEE Tansactions on Electonic Computes, vol EC-8, no 8, pp 0-, Septembe 959 Wang, Y; Tang, Y; Jiang, Y; Chung, J; Song, S & Lim, M (007) Novel Memoy Refeence Reduction Methods fo FFT Implementations on DSP Pocessos IEEE Tansactions on Signal Pocessing, vol 55, no 5, pp 8-9, May 007 Wey, C; Lin, S & Tang, W (007) Efficient Memoy-Based FFT Pocessos Fo OFDM Applications IEEE Intenational Confeence on Electo- Infomation Technology, pp5-50, May 007 Xiao, X; Ouklu, E & Saniie, J (008) An Efficient FFT Engine with Reduced Addessing Logic IEEE Tansactions on Cicuits and Systems II: Expess Biefs, vol 55, no, pp9-5, Novembe 008 Xiao, X; Ouklu, E & Saniie, J (009) Fast Memoy Addessing Scheme fo Radix- FFT Implementation IEEE Intenational Confeence on Electo/Infomation Technology, EIT 009, pp 7-0, June 009 Xiao, X; Ouklu, E & Saniie, J (00) Reduced Memoy Achitectue fo CORDICbased FFT IEEE Intenational Symposium on Cicuits and Systems (ISCAS), June 00 wwwintechopencom

25 0 Fouie Tansfoms - Appoach to Scientific Pinciples Yang, L; Zhang, K; Liu, H; Huang, J & Huang, S (006) An Efficient Locally Pipelined FFT Pocesso IEEE Tansactions on Cicuits and Systems II, Exp Biefs, vol 5, issue 7, pp , July 006 Zainal, M S; Yoshizawa, S & Miyanaga, Y (009) Low Powe FFT Design fo Wieless Communication Systems Intenational Symposium on Intelligent Signal Pocessing and Communications Systems ISPACS 008, pp -, Febuay 009 wwwintechopencom

26 Fouie Tansfoms - Appoach to Scientific Pinciples Edited by Pof Goan Nikolic ISBN Had cove, 68 pages Publishe InTech Published online, Apil, 0 Published in pint edition Apil, 0 This book aims to povide infomation about Fouie tansfom to those needing to use infaed spectoscopy, by explaining the fundamental aspects of the Fouie tansfom, and techniques fo analyzing infaed data obtained fo a wide numbe of mateials It summaizes the theoy, instumentation, methodology, techniques and application of FTIR spectoscopy, and impoves the pefomance and quality of FTIR spectophotometes How to efeence In ode to coectly efeence this scholaly wok, feel fee to copy and paste the following: Edal Ouklu, Jafa Saniie and Xin Xiao (0) Reduced Logic and Low-Powe FFT Achitectues fo Embedded Systems, Fouie Tansfoms - Appoach to Scientific Pinciples, Pof Goan Nikolic (Ed), ISBN: , InTech, Available fom: InTech Euope Univesity Campus STeP Ri Slavka Kautzeka 8/A 5000 Rijeka, Coatia Phone: +85 (5) Fax: +85 (5) wwwintechopencom InTech China Unit 05, Office Block, Hotel Equatoial Shanghai No65, Yan An Road (West), Shanghai, 0000, China Phone: Fax:

27 0 The Autho(s) Licensee IntechOpen This chapte is distibuted unde the tems of the Ceative Commons Attibution-NonCommecial- ShaeAlike-0 License, which pemits use, distibution and epoduction fo non-commecial puposes, povided the oiginal is popely cited and deivative woks building on this content ae distibuted unde the same license