CSE4201. Computer Architecture

Transcription

1 CSE 4201 Compute Achitectue Pof. Mokhta Aboelaze Pats of these slides ae taken fom Notes by Pof. David Patteson at UCB Outline MIPS and instuction set Simple pipeline in MIPS Stuctual and data hazads Fowading Banching Exception and inteupts Multicycle opeations 1

2 MIPS Instuction set 32-bit fixed fomat instuction (3 fomats) bit GPR (R0 contains zeo, DP take pai) 3-addess, eg-eg aithmetic instuction Single addess mode fo load/stoe: base + displacement no indiection Simple banch conditions Delayed banch Instuction Set Instuction Set Achitectue Defines set of opeations, instuction fomat, hadwae suppoted data types, named stoage, addessing modes, sequencing Meaning of each instuction is descibed by RTL on achitected egistes and memoy Given technology constaints assemble adequate datapath Achitected stoage mapped to actual stoage Function units to do all the equied opeations Possible additional stoage (eg. MAR, MBR, ) Inteconnect to move infomation among egs and FUs Map each instuction to sequence of RTLs Collate sequences into symbolic contolle state tansition diagam (STD) Lowe symbolic STD to contol points Implement contolle 2

3 MIPS Instuction Set Op MIPS Instuction Set iste-iste Rs1 iste-immediate Rs Op Rs1 Rd immediate Banch Op taget Rd Opx Op Rs1 Rs2/Opx immediate Jump / Call 3

4 Next PC MIPS 5-Stage Pipeline Instuction Fetch 4 Adde Inst. Decode. Fetch Next SEQ PC RS1 Execute Add. Calc Zeo? Memoy Access MUX Wite Back Addess Memoy Inst RS2 RD File MUX MUX Data Memoy L M D MUX IR <= mem[pc]; PC <= PC + 4 Imm Sign Extend [IR d ] <= [IR s ] op IRop [IR t ] WB Data Next PC Instuction Fetch 4 Adde 5-stage Pipeline Inst. Decode. Fetch Next SEQ PC RS1 Execute Add. Calc Next SEQ PC Zeo? Memoy Access MUX Wite Back Addess Memoy IR <= mem[pc]; /ID RS2 File ID/ MUX MUX /MEM Data Memoy MEM/WB MUX PC <= PC + 4 A <= [IR s ]; B <= [IR t ] slt <= A op IRop B WB <= slt [IR d ] <= WB Imm Sign Extend RD RD RD WB Data 4

5 MIPS 5-Stage Pipeline IR <= mem[pc]; PC <= PC + 4 JSR JR b if bop(a,b) jmp PC <= IR jadd A <= [IR s ]; opfetch-dcd B <= [IR t ] RR RI <= A op IRop B <= A op IRop IR im LD <= A + IR im ST PC <= PC+IR im WB <= WB <= WB <= Mem[] [IR d ] <= WB [IR d ] <= WB [IR d ] <= WB Next PC 5 Steps of MIPS Datapath Instuction Fetch 4 Adde Figue A.3, Page A-9 Inst. Decode. Fetch Next SEQ PC RS1 Execute Add. Calc Next SEQ PC Zeo? Memoy Access MUX Wite Back Addess Memoy /ID RS2 File ID/ MUX MUX /MEM Data Memoy MEM/WB MUX Imm Sign Extend RD RD RD WB Data Data stationay contol local decode fo each instuction phase / pipeline stage 5

6 Visualizing Pipelining Figue A.2, Page A-8 Time (clock cycles) I n s t. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 O d e Pipelining is not quite that easy! Limits to pipelining: Hazads pevent next instuction fom executing duing its designated clock cycle Stuctual hazads: HW cannot suppot this combination of instuctions (single peson to fold and put clothes away) Data hazads: Instuction depends on esult of pio instuction still in the pipeline (missing sock) Contol hazads: Caused by delay between the fetching of instuctions and decisions about changes in contol flow (banches and jumps). 6

7 One Memoy Pot/Stuctual Hazads Time (clock cycles) Figue A.4, Page A-14 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t. O d e Load Inst 1 Inst 2 Inst 3 Inst 4 One Memoy Pot/Stuctual Hazads Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t. O d e Load Inst 1 Inst 2 Stall Inst 3 Bubble Bubble Bubble Bubble Bubble How do you bubble the pipe? 7

8 Speed Up Equation fo Pipelining CPI pipelined = Ideal CPI + Aveage Stall cycles pe Inst Ideal CPI Pipeline depth Speedup = Ideal CPI + Pipeline stall CPI Cycle Cycle Time Time unpipelined pipelined Fo simple RC pipeline, CPI = 1: Pipeline depth Speedup = 1 + Pipeline stall CPI Cycle Cycle Time Time unpipelined pipelined Example: Dual-pot vs. Single-pot Machine A: Dual poted memoy ( Havad Achitectue ) Machine B: Single poted memoy, but its pipelined implementation has a 1.05 times faste clock ate Ideal CPI = 1 fo both Loads ae 40% of instuctions executed SpeedUp A = Pipeline Depth/(1 + 0) x (clock unpipe /clock pipe ) = Pipeline Depth SpeedUp B = Pipeline Depth/( x 1) x (clock unpipe /(clock unpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUp A / SpeedUp B = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 Machine A is 1.33 times faste 8

9 Data Hazad on R1 Figue A.6, Page A-17 Time (clock cycles) ID/RF MEM WB I n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11 Thee Geneic Data Hazads Read Afte Wite (RAW) Inst J ties to ead opeand befoe Inst I wites it I: add 1,2,3 J: sub 4,1,3 Caused by a Dependence (in compile nomenclatue). This hazad esults fom an actual need fo communication. 9

10 Thee Geneic Data Hazads Wite Afte Read (WAR) Inst J wites opeand befoe Inst I eads it I: sub 4,1,3 J: add 1,2,3 K: mul 6,1,7 Called an anti-dependence by compile wites. This esults fom euse of the name 1. Can t happen in MIPS 5 stage pipeline because: All instuctions take 5 stages, and Reads ae always in stage 2, and Wites ae always in stage 5 Thee Geneic Data Hazads Wite Afte Wite (WAW) Inst J wites opeand befoe Inst I wites it. I: sub 1,4,3 J: add 1,2,3 K: mul 6,1,7 Called an output dependence by compile wites This also esults fom the euse of name 1. Can t happen in MIPS 5 stage pipeline because: All instuctions take 5 stages, and Wites ae always in stage 5 Will see WAR and WAW in moe complicated pipes 10

11 I n s t. Fowading to Avoid Data Hazad add 1,2,3 sub 4,1,3 Time (clock cycles) O d e and 6,1,7 o 8,1,9 xo 10,1,11 HW Change fo Fowading NextPC istes ID/ mux mux /MEM Data Memoy MEM/WR Immediate mux What cicuit detects and esolves this hazad? 11

12 I n s t. O d e Fowading to Avoid LW-SW Data Hazad add 1,2,3 lw 4, 0(1) sw 4,12(1) o 8,6,9 Time (clock cycles) xo 10,9,11 Data Hazad Even with Fowading Time (clock cycles) I n s t. lw 1, 0(2) sub 4,1,6 O d e and 6,1,7 o 8,1,9 12

13 Data Hazad Even with Fowading Time (clock cycles) I n s t. O d e lw 1, 0(2) sub 4,1,6 and 6,1,7 Bubble Bubble o 8,1,9 Bubble How is this detected? Softwae Scheduling to Avoid Load Hazads Ty poducing fast code fo a = b + c; d = e f; assuming a, b, c, d,e, and f in memoy. Slow code: LW LW ADD SW LW LW SUB SW Rb,b Rc,c Ra,Rb,Rc a,ra Re,e Rf,f Rd,Re,Rf d,rd Fast code: LW LW LW ADD LW SW SUB SW Rb,b Rc,c Re,e Ra,Rb,Rc Rf,f a,ra Rd,Re,Rf d,rd Compile optimizes fo pefomance. Hadwae checks fo safety. 13

14 Contol Hazad on Banches Thee Stage Stall 10: beq 1,3,36 14: and 2,3,5 18: o 6,1,7 22: add 8,1,9 36: xo 10,1,11 What do you do with the 3 instuctions in between? How do you do it? Whee is the commit? Banch Stall Impact If CPI = 1, 30% banch, Stall 3 cycles => new CPI = 1.9! Two pat solution: Detemine banch taken o not soone, AND Compute taken banch addess ealie MIPS banch tests if egiste = 0 o 0 MIPS Solution: Move Zeo test to ID/RF stage Adde to calculate new PC in ID/RF stage 1 clock cycle penalty fo banch vesus 3 14

15 Next PC Pipelined MIPS Datapath Instuction Fetch 4 Adde Figue A.24, page A-38 Inst. Decode. Fetch Next SEQ PC RS1 Adde MUX Zeo? Execute Add. Calc Memoy Access Wite Back Addess Memoy /ID RS2 File ID/ MUX /MEM Data Memoy MEM/WB MUX Imm Sign Extend RD RD RD WB Data Inteplay of instuction set design and cycle time. Fou Banch Hazad Altenatives #1: Stall until banch diection is clea #2: Pedict Banch Not Taken Execute successo instuctions in sequence Squash instuctions in pipeline if banch actually taken Advantage of late pipeline state update 47% MIPS banches not taken on aveage PC+4 aleady calculated, so use it to get next instuction #3: Pedict Banch Taken 53% MIPS banches taken on aveage But haven t calculated banch taget addess in MIPS MIPS still incus 1 cycle banch penalty Othe machines: banch taget known befoe outcome 15

16 Fou Banch Hazad Altenatives #4: Delayed Banch Define banch to take place AFTER a following instuction banch instuction sequential successo 1 sequential successo 2... sequential successo n banch taget if taken Banch delay of length n 1 slot delay allows pope decision and banch taget addess in 5 stage pipeline MIPS uses this Scheduling Banch Delay Slots A. Fom befoe banch B. Fom banch taget C. Fom fall though add $1,$2,$3 if $2=0 then delay slot sub $4,$5,$6 add $1,$2,$3 if $1=0 then delay slot A is the best choice, fills delay slot & educes instuction count (IC) In B, the sub instuction may need to be copied, inceasing IC In B and C, must be okay to execute sub when banch fails add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes if $2=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 add $1,$2,$3 if $1=0 then sub $4,$5,$6 16

17 Delayed Banch Compile effectiveness fo single banch delay slot: Fills about 60% of banch delay slots About 80% of instuctions executed in banch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Banch downside: As pocesso go to deepe pipelines and multiple issue, the banch delay gows and need moe than one delay slot Delayed banching has lost populaity compaed to moe expensive but moe flexible dynamic appoaches Gowth in available tansistos has made dynamic appoaches elatively cheape Evaluating Banch Altenatives Pipeline speedup = Pipeline depth 1 +Banch fequency Banch penalty Assume 4% unconditional banch, 6% conditional banch- untaken, 10% conditional banch-taken SchedulingBanchCPIspeedup v.speedup v. scheme penalty unpipelined stall Stall pipeline Pedict taken Pedict not taken Fall Delayed 07 banch

18 Poblems with Pipelining Exception: An unusual event happens to an instuction duing its execution Examples: divide by zeo, undefined opcode Inteupt: Hadwae signal to switch the pocesso to a new instuction steam Example: a sound cad inteupts when it needs moe audio output samples (an audio click happens if it is left waiting) Poblem: It must appea that the exception o inteupt must appea between 2 instuctions (I i and I i+1 ) The effect of all instuctions up to and including I i is totally complete No effect of any instuction afte I i can take place The inteupt (exception) handle eithe abots pogam o estats at instuction I i+1 And In Conclusion: Contol and Pipelining Quantify and summaize pefomance Ratios, Geometic Mean, Multiplicative Standad Deviation F&P: Benchmaks age, disks fail,1 point fail dange Contol VIA State Machines and Micopogamming Just ovelap tasks; easy if tasks ae independent Speed Up Pipeline Depth; if ideal CPI is 1, then: Pipeline depth Cycle Time Speedup = 1 + Pipeline stall CPI Cycle Time unpipelined pipelined Hazads limit pefomance on computes: Stuctual: need moe HW esouces Data (RAW,WAR,WAW): need fowading, compile scheduling Contol: delayed banch, pediction Exceptions, Inteupts add complexity 18

19 Multicycle opeations Moe than one function unit, each equie a vaiable numbe of cycles. INT FP/* ID MEM WB FP+ FP/ / Multi cycles opeations Assuming the following Function Unit latency initiation peiod Intege 0 1 Data Memoy 1 1 FP add 3 1 FP Multiply 6 1 FP Divide Notice that FP add and multiply ae pipelined (4 and 7 stages pipeline espectively). Latency is the numbe of cycles between an instuction that poduces a esult and anothe one that uses the esult. 19

20 Multicycle opeations MULTD ID M1 M2 M3 M4 M5 M6 M7 MEM WB ADDD ID A1 A2 A3 A4 MEM WB LD ID MEM WB SD ID MEM WB Stages in ed indicates when data ae needed, in blue indicates when data ae poduced Need to intoduce moe pipeline egistes A1/A2,.. 20

21 Hazads and Fowading Because the divide unit is not pipelined, stuctual hazads may aise Because of diffeent unning times. We may need to do moe than one egiste wite in a single cycle WAW hazad is now possible, WAR is not since they all ead in one stage Instuctions can complete in diffeent ode, moe complicated exception handling Because of the longe latency, moe RAW hazad Hazads and Fowading Instuction LD F4,0(R2) ID MEM WB MUL F0,F4,F6 ID S M1 M2 M3 M4 M5 M6 M7 MEM WB ADDD F2,F0,F8 ID S S S S S S S A1 A2 A3 A4 SD F2,0(R2) ID S S S S S S S S S S MEM Substantially longe stall and fowading 21

22 Hazad and Fowading Instuction MULTD F0,F4,F6 ID M1 M2 M3 M4 M5 M6 M7 MEM WB.. ADDD F2,F4,F6 ID A1 A2 A3 A4 MEM WB LD F8,0(R2) ID MEM WB Thee diffeent instuction witing in the same cycle, LD is issued one cycle ealie, with destination of F2, that will lead to WAW hazad Hazads and Fowading One way to deal with multiple wites is to have multiple wite pots, but it may be aely used. Anothe way is to detect the stuctual hazad by using an intelock 1. We can tack the use of the wite pot befoe it is issued (ID stage) and stall 2. O, we can detect this hazad at enteing the MEM stage, it is easie to detect, and we can choose which instuction to poceed (the one with the longest latency?) 22

23 Maintaining Pecise Exception DIVF F0,F2,F4 ADDF F10,F10,F8 SUBF F12,F12,F14 This is known as out of ode completion What if SUBF causes an Exception afte ADDF is completed but befoe DIVF is, o if DIVF caused an exception afte both ADDF and SUBF completed, thee is no way to maintain a pecise exception since ADDF destoys one of its opeands Maintaining Pecise Exception (sol 1) Ealy solution is to ignoe the poblem Moe ecent ones, ae to intoduce two modes of opeations, fast but with impecise exception, and slow with pecise exception. DEC Alpha 2104, Powe1 and Powe-2, MIPS R

24 Maintaining Pecise Exception (sol 2) Buffe the esults of an opeation until all the opeations befoe it ae completed. Costly, especially with long pipes. One vaiation is called histoy file, old values ae stoed in the histoy file and can be estoed in case of exception O, we an use futue file, whee new values ae stoed until all poceeding instuctions ae completed. Maintaining Pecise Exception (sol 3) Allow the exception to become impecise, but we have to keep enough infomation so that the exception handling outine can ecove. These infomation ae usually the PC addesses of the instuctions that wee in the pipe duing the exception, who finished, and who not. 24

25 Maintaining Pecise Exception (sol 4) A hybid technique, Allow the instuctions to be issued only if we ae cetain that all the instuctions befoe the issuing instuction will complete without causing an exception That guaantees that no instuction afte the inteupting one will be completed, and all instuctions befoe it will complete. Must check fo exception ealy in the stage. MIPS Stage Pipeline: fist half of fetching of instuction; PC selection happens hee as well as initiation of instuction cache access. second half of access to instuction cache. RF instuction decode and egiste fetch, hazad checking and also instuction cache hit detection. execution, which includes effective addess calculation, opeation, and banch taget computation and condition evaluation. DF data fetch, fist half of access to data cache. DS second half of access to data cache. TC tag check, detemine whethe the data cache access hit. WB wite back fo loads and egiste-egiste opeations. 8 Stages: What is impact on Load delay? Banch delay? Why? 25

26 MIPS cycle load delay (data is eady afte DS) RF RF DF RF DS DF RF TC DS DF RF WB TC DS DF RF 3 cycles banch delay, MIOS4000 has a singly cycle banch delay scheduling with a pedict taken fo the emaining 2 RF RF DF RF DS DF RF TC DS DF RF WB TC DS DF RF MIPS4000 FP Pipeline FP Adde, FP Multiplie, FP Divide Last step of FP Multiplie/Divide uses FP Adde HW 8 kinds of stages in FP units: Stage Functional unit Desciption A FP adde Mantissa ADD stage D FP divide Divide pipeline stage E FP multiplie Exception test stage M FP multiplie Fist stage of multiplie N FP multiplie Second stage of multiplie R FP adde Rounding stage S FP adde Opeand shift stage U Unpack FP numbes 26

27 MIPS4000 F P Pipeline FP Inst Pipeline stages Add, Subtact U,S+A,A+R,R+S Multiply U,E+M,M,M,M,N,N+A,R Divide U,A,R,D 28,D+A,D+R, D+R, D+A, D+R, A, R Squae oot U,E,(A+R) 108,A,R Negate U,S Absolute value U,S FP compae U,A,R OP Latency Initiation inteval ADD,SUB 4 3 MUL 8 4 DIV SQRT NEG,ABS 2 1 COMP 3 2 AMPLE MUL SUE MUL Issue U M M M M N N,A R ADD Issue U S,A A,R R,S ADD Issue U S,A A,R R,S ADD Stall U S,A A,R R,S ADD Stall U S,A A,R R,S ADD Issue U S,A A,R R,S ADD Issue U S,A A,R R,S ADD Issue U S,A A,R R,S The inteaction between a multiply issued at time 0, and add issued between 1 and 7, in all except 2 we can poceed without stalls, in these two we have to stall 27