Administrivia. CMSC 411 Computer Systems Architecture Lecture 5. Data Hazard Even with Forwarding Figure A.9, Page A-20

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1 Administivia CMSC 411 Compute Systems Achitectue Lectue 5 Basic Pipelining (cont.) Alan Sussman als@cs.umd.edu as@csu dedu Homewok poblems fo Unit 1 due today Homewok poblems fo Unit 3 posted soon CMSC (fom Patteson) 2 Fowading to Avoid - Data Hazad Figue A.8, Page A-29 Data Hazad Even with Fowading Figue A.9, Page A-20 Time (clock cycles) I n s t. O d e add 1,2,3 lw 4, 0(1) sw 4,12(1) 1 o 8,6,96 9 xo 10,9,11 AL LU Time (clock cycles) I lw 1, 0(2) R n s t sub 4,1,61 6. O d e and 6,1,71 7 o 8,1,91 9 AL LU AL LU CMSC (fom Patteson) 3 CMSC (fom Patteson) 4

2 Data Hazad Even with Fowading (Simila to Figue A.10, Page A-21) Softwae Scheduling Instead I n s t. Time (clock cycles) s lw 1, 0(2) O d e sub 4,1,6, and 6,1,7 o 8,1,9 Bubble Bubble Bubble Ty poducing fast code fo a = b + c; d = e f; assuming a, b, c, d,e, and f in memoy. Slow code: ADD SUB Rb,b Rc,c Ra,Rb,Rc a,ra Re,e Rf,f Rd,Re,Rf d,rd Fast code: ADD SUB Rb,b Rc,c Re,e Ra,Rb,Rc Rf,f a,ra Rd,Re,Rf d,rd Compile optimizes fo pefomance. Hadwae checks fo safety. CMSC (fom Patteson) 5 CMSC (fom Patteson) 6 Contol hazads Question: When do we find out that the PC needs to be modified? Answe: In pipeline stage ID of a banch instuction So, if a banch is not-taken (i.e., if the PC is not modified), need a one-cycle delay Question: When is a taken banch s addess known? used to compute, so EX stage Need two (o thee) cycle delay Example If banch in 30% of instuctions, then instead of executing 1 instuction pe cycle, have 70% of instuctions ti executing in 1 cycle and 30% of instuctions executing in 2 cycles An aveage of = 1.3 cycles pe instuction Wose by 30% CMSC (fom Patteson) 7 CMSC (fom Patteson) 8

3 Contol Hazad on Banches Thee Stage Stall Banch Stall Impact 10:beq 1,3,34 14:and 2,3,5 18:o 6,1,7 22:add 8,1,9 34:xo 10,1,11 If CPI = 1, 30% banch, Stall 3 cycles => new CPI = 1.9! Two pat solution: Detemine banch taken o not taken soone, AND Compute taken banch addess ealie MIPS banch tests if egiste = 0 o 0 MIPS Solution: Move Zeo test to ID/RF stage Adde to calculate new PC in ID/RF stage 1 clock cycle penalty fo banch vesus 3 What do you do with the 3 instuctions in between? How do you do it? Whee is the commit? CMSC (fom Patteson) 9 CMSC (fom Patteson) 10 Pipelined MIPS Datapath Figue A.24, page A-38 Next PC Addes ss Instuction Fetch 4 Adde Memo y IF/ ID Inst. Decode. Fetch Next SEQ PC Adde RS1 RS2 MUX Zeo? F ile Sign Extend Imm ID/E X Execute Add. Calc MUX EX/ME EM RD RD RD Memoy Access Data Me emoy MEM/W WB Wite Back MUX ata WB D Fou Banch Hazad Altenatives #1: Stall until banch diection is clea #2: Pedict Banch Not Taken Execute successo instuctions in sequence Squash instuctions in pipeline if banch actually taken Advantage of late pipeline state update 47% MIPS banches not taken on aveage PC+4 aleady calculated, so use it to get next instuction #3: Pedict Banch Taken 53% MIPS banches taken on aveage But haven t calculated banch taget addess in MIPS» MIPS still incus 1 cycle banch penalty» Othe machines: banch taget known befoe outcome Inteplay of instuction set design and cycle time. CMSC (fom Patteson) 11 CMSC (fom Patteson) 12

4 Fou Banch Hazad Altenatives #4: Delayed Banch Define banch to take place AFTER a following instuction banch instuction sequential successo 1 sequential successo 2... Banch delay of length n sequential successo n banch taget if taken 1 slot delay allows pope decision and banch taget addess in 5 stage pipeline MIPS uses this CMSC (fom Patteson) 13 Scheduling Banch Delay Slots (Fig A.14) A. Fom befoe banch B. Fom banch taget C. Fom fall though sub R4,R5,R6 if R2=0 then delay slot delay slot delay slot sub R4,R5,R6R5 R6 becomes becomes becomes if R2=0 then sub R4,R5,R6 sub R4,R5,R6 A is the best choice, fills delay slot & educes instuction count (IC) In B, the sub instuction may need to be copied, inceasing IC In B and C, must be okay to execute sub when banch fails CMSC (fom Patteson) 14 Scheduling banch delay slot Delayed Banch If taken fom befoe banch banch must not depend on escheduled instuction always impoves pefomance If taken fom banch taget must be OK to execute escheduled instuctions if banch not taken, and may need to duplicate insts. pefomance impoved when banch taken If taken fom fall though must be OK to execute insts. if banch taken impoves pefomance when banch not taken Compile effectiveness fo single banch delay slot: Fills about 60% of banch delay slots About 80% of instuctions executed in banch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Banch downside: As pocesso go to deepe pipelines and multiple issue, the banch delay gows and need moe than one delay slot Delayed banching has lost populaity compaed to moe expensive but moe flexible dynamic appoaches Gowth in available tansistos has made dynamic appoaches elatively cheape CMSC (fom Patteson) 15 CMSC (fom Patteson) 16

5 Evaluating Banch Altenatives Pipeline speedup = Pipeline depth 1 +Banch fequency Banch penalty Assume: 4% unconditional banch, 6% conditional banch- untaken, 10% conditional banch-taken Scheduling Banch CPI speedup v. speedup v. scheme penalty unpipelined stall Stall pipeline Pedict taken Pedict not taken Delayed banch Pipelining Summay Pipelining can speed instuction execution (thoughput) But need to deal with stuctual hazads, data hazads, and contol hazads Next How to handle exceptions? How to handle long instuctions, such as floating point aithmetic? CMSC (fom Patteson) 17 CMSC (fom Patteson) 18 The poblem Question: What makes pipelining had to implement? Answe: Supises Technical names fo supises: exceptions faults inteupts Some examples of exceptions Request fo I/O Aithmetic toubles: oveflow o undeflow Page fault: data not in (physical) memoy Illegal addess, giving a memoy potection violation Hadwae failue CMSC (fom Patteson) 19 CMSC (fom Patteson) 20

6 Classifying exceptions Synchonous: epeatable evey time Example: DIV R2, R2, R0 Asynchonous: caused by extenal events like hadwae failue and devices extenal to pocesso and memoy Use equested: use task asks fo it (example: beakpoint) Coeced: cannot be pedicted by use Use maskable: can be disabled by use task Example: aithmetic exception Nonmaskable: cannot be tuned off Example: hadwae failue Classifying exceptions (cont.) Within instuction: pevents instuction fom completing Between instuctions: ti no instuction ti pevented Teminating: stops the task Resuming: task can continue Machines that handle exceptions, save the state, and then estat coectly ae said to be estatable CMSC (fom Patteson) 21 CMSC (fom Patteson) 22 Categoizing exceptions Fig. A. 27 Exception type Synch. vs. asynch. Use equest vs. coece Use maskable vs. not Within vs. between instuctions Resume vs. teminate I/O device Asynch Coeced Not Between Resume equest Invoke OS Synch Use eq. Not Between Resume Tacing instuctions Synch Use eq. Maskable Between Resume Beakpoint Synch Use eq. Maskable Between Resume Intege oveflow Synch Coeced Maskable Within Resume Floating pt. Synch Coeced Maskable Within Resume oveflow/ undeflow Categoizing exceptions (cont.) Exception type Synch. vs. asynch. Use equest vs. coece Use maskable vs. not Within vs. between instuctions Resume vs. teminate Page fault Synch Coeced Not Within Resume Misaligned memoy access Mem. pot. violation Synch Coeced Maskable Within Resume Synch Coeced Not Within Resume Undefined Synch Coeced Not Within Teminate instuction Hadwae malfunction Powe failue Asynch Coeced Not Within Teminate Asynch Coeced Not Within Teminate CMSC (fom Patteson) 23 CMSC (fom Patteson) 24

7 The most difficult exceptions ae those that occu within EX o MEM stages and need to be handled in a estatable way Why difficult? Handling one includes: the next IF gets a "tap instuction" until the tap is taken, tun off all "wites" fo the faulting instuction and those that follow it what does the tap do?» The tap tansfes contol to the exception handling outine in the opeating system, which saves the PC of the faulting instuction and handles the fault the task is then esumed, using the saved PC and the MIPS instuction RFE o something like it Note: May need to save seveal PCs if delayed banches ae involved Exceptions (cont.) Ideally, pipeline can be inteupted so that instuctions befoe the fault complete. Then want to estat t execution just afte the faulting instuction - pecise exception handling This is the ight way to do it, but sometimes achitects/manufactues take shotcuts CMSC (fom Patteson) 25 CMSC (fom Patteson) 26