Full-IC manufacturability check based on dense silicon imaging

Transcription

1 Science in China Ser. F Information Sciences 2005 Vol.48 No Full-IC manufacturability check based on dense silicon imaging YAN Xiaolang, SHI Zheng, CHEN Ye, MA Yue & GAO Gensheng Institute of VLSI Design, Zhejiang University, Hangzhou , China Correspondence should be addressed to Chen Ye ( chenye@vlsi.zju.edu.cn) Received January 10, 2005 Abstract With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-ret sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-ret verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well. Keywords: RET, OPC, PSM, design for manufacturability, photolithography simulation. DOI: /04yf0115 State of the art IC manufacturing process is witnessing the situation that the wavelength of stepper is more than twice the minimum feature size (193 nm wavelength vs. 90 nm/65 nm/45 nm feature size). According to the International Technology Roadmap for Semiconductors, this reality of sub-wavelength lithography will continue for the next several technology nodes. Optical Proximity Effect (OPE), as a technical terminology, usually refers to all of the undesired pattern vs. layout distortions caused by mask making, optical lithography and etching. To compensate OPE for better manufacturability, various Reticle Enhancement Technology (RET) methods based on layout correction and mask phase assigning have emerged. Consequently, Optical Proximity Correction (OPC), Phase-Shifting Masks (PSM) and Scattering Bars Insertion (SBI) become three basic categories of RETs. In state of the art IC designs, these RET methods are used in concert to maximally improve the quality of pattern transfer under environment with OPE. The ever increasing complexity of RET design methodology brings about a dramatic increase in the final layout complexity and mask making expense. This reality demands us to perform sign-off checks for various types of potential errors to ensure the

2 534 Science in China Ser. F Information Sciences 2005 Vol.48 No full correctness of post-ret layouts before mask writing [1 3]. Among all these types of manufacturability checks, some have to be carried out by using information from Dense Silicon Imaging (DSI). In Fig. 1(a), we show a small area of original 90 nm design with corresponding post-opc layouts and an inserted scattering bar. The mask type is attenuated PSM (attpsm). Simulated contours by DSI are shown in Fig. 1(b). The dotted lines indicate the surely printable areas (threshold = 0.3) while the solid lines indicate the contours for possibly printable areas (threshold = 0.15). Although the original layout is compliant with geometric Design Rule Check (DRC) and the desired features are enhanced by RET modifications, islands of nearly printable area also arise which might be printed with a slight shifting of process window. These undesired features would probably cause inaccurate circuit characteristics or even bridging malfunction [4]. Besides, intensity contrasts on some feature edges are still low after applying RETs, which also increase manufacture variability. Fig. 1. (a) Pre-RET and post-ret layouts; (b) simulation result The example in Fig. 1 shows the importance of paying close attention to environment disturbance when applying RET corrections as well as the worth of performing manufacturability verifications based on DSI as a sign-off step before mask making. Simply because a practical full-chip RET scheme is unable to take care of all side effects of corrections, sign-off verification step is highly needed. In a recently published paper [5], we have summarized the major limitations of prevailing RET schemes, and described the architecture of an effective sign-off verification tool based on Sparse Aerial Imaging (SAI). However, in this paper, we focus on sign-off verifications based on DSI, with the emphases on algorithms and applications for putting such verifications into practice. In the following, section 1 describes conventional RET and verification methodology as well as the lithographic modeling framework we choose. In section 2, key algorithms for full-chip scale DSI, including kernel expansion, element block partition, fast transformation of element block and a specialized 2-D FFT scheme are presented. Section 3 describes an application of full-ic manufacturability check based on our DSI algorithms in an experiment with the presence of low contrast area. Conclusion is given in section 4. 1 Modeling and post-ret verification methodology The three main components of RET, namely OPC, PSM and SBI, are well studied in many recent publications. To apply RETs, a physical model describing the target process

3 Full-IC manufacturability check based on dense silicon imaging 535 needs to be calibrated to real wafer data. Applying alternating PSM (altpsm) needs an additional step of non-conflicting phase assignment. After that, critical layout features are segmented and corrected according to criteria either from local pattern matching (Rule-based OPC) or from silicon contour simulation (Model-based OPC). Scattering bars and dummy features for CMP purpose, if any, are usually inserted before the correction step [6,7]. A critical issue for applying RET and post-ret verification is to have a fast enough simulation engine which can predict the mask to silicon pattern transfer in reasonable accuracy. The vast physical complexities of OPE, due to many process steps from mask writing to etching, make this a daunting task. Nevertheless, except for process steps designed for intentional pattern distortion such as over-etching, optical lithography has been identified as the major source of OPE, while other sources can be approximated by some first-order linear filters within acceptable accuracy. In practice, OPE is usually characterized by a semi-empirical bi-linear model which uses Hopkins Equation containing empirically fitted parameters to calculate Pseudo-Intensities. Final silicon patterns are then determined by constant or variable thresholding on the Pseudo-Intensities [8 10]. This imaging procedure, dependent not on pure optical aerial intensities but on Pseudo-Intensities describing most OPE sources, is termed Silicon Imaging throughout this paper. Hopkins Equation can be expressed in space domain or frequency domain. Eq. (1) lists both of the forms, where I (x, y) and I (f, g) are Pseudo-Intensities, F(x, y) and F(f, g) are mask transmissions. The mask-independent Transmission Cross-Coefficients which describe the whole lithographic flow, are TCC(x 1, y 1 ; x 2, y 2 ) and TCC(f 1, g 1 ; f 2, g 2 ) in space domain and frequency domain, respectively (1a) I( x, y) = F( x, y ) F( x, y ) TCC( x x, y y ; x x, y y ) dx dy dx dy, (1b) I( f, g) = F( f, g ) F( f + f, g + g) TCC( f, g ; f + f, g + g) df dg, 2 i (2) i I( xy, ) = ( Fxy (, ) K0 ( xy, )). Since feature edges are sparsely distributed in a layout, space domain calculation is preferred both by model characterization and OPC procedures. For the kernel-based convolution [5,8,11,12] method listed in eq. (2), a set of 2-D kernels {K0 i } are generated. The sum of the products of these kernels is an approximation to the 4-D transferring function of the bi-linear system. The intensity of one spatial point is calculated by square sum of the convolutions of mask and these kernels. In Table 1, more than 400 test points measured from a real 0.13 μm process are compared to simulation results from our improved kernel-based model calibrated to this process. Relative errors on test points are within the range of +/ 10%, which convincingly suggests the effectiveness of the whole modeling methodology.

4 536 Science in China Ser. F Information Sciences 2005 Vol.48 No Table 1 Results by calibrated modeling for a 0.13 μm poly layer process Average prediction error /nm Maximum prediction error /nm Standard deviation of errors /nm Calibrated model-line Calibrated model-butt Total measured test points 431 This modeling and intensity computing approach, which is now used in OPC tools for edge-based simulation and manipulation, also affects the methodology of post-ret verification. Currently, a practical post-ret verification flow typically employs a mixture of methods such as DRC based on RET-aware geometrical comparison and ORC (Optical Rule Check) based on sparse points imaging. This mixed method has shown great advantages in finding post-ret problems on specific sites such as MOSFET channels and poly-si line-ends. Tools fully dedicated to doing this kind of feature-centric verifications, which may include channel distortion, contact enclosure and many other items on the checklist, have appeared recently [2,5,13]. On the other hand, feature-centric verification does not handle well certain kinds of manufacturability problems such as what have been shown in Fig. 1(b). For layouts corrected by a combination of OPC, PSM and especially SBI, many small size features are added which may introduce undesirable effects not being easily detected by sparse points imaging method without significant performance penalty. Consequently, even though large portions of the imaged points might be irrelevant to manufacturability problems, a full-chip verification based on DSI is necessary to locate such problematic areas. In fact, methods of Dense Aerial Imaging (DAI) were studied intensively before the emergence of Sparse Aerial Imaging methods. The implementations in space domain or frequency domain can be found in simulators such as SPLAT [14 17]. Certain simulation speed has been achieved by using conventional accelerating algorithms such as FFT in these methods [15 17]. In the next section, a significantly improved scheme of fast DSI, which makes full-chip scale imaging practical, is introduced with most of its key algorithms. 2 Algorithms for full-chip dense imaging A set of convolution kernels {K0 i } characterized for sparse points imaging as in eq. (2), which describe the pattern transferring characteristic of a specific litho-flow in a certain degree of accuracy, are assumed to be ready before our dense points silicon imaging. By using these kernels, our scheme can have good compatibility with kernelbased method in prevailing OPC and feature-centric verification tools. 2.1 Building TCC in frequency domain The new imaging method is based on frequency domain computations compliant with eq. (1b) to exploit the simplicity of multiplication in frequency domain in comparison with convolution in space domain. Frequency domain TCC in eq. (1b) can be rebuilt by

5 Full-IC manufacturability check based on dense silicon imaging 537 the calibrated convolution kernels, as listed in eq. (3), where FT[ ] denotes Fourier Transform. 2.2 Kernel expansion * T i i (3) i TCC( f, g ; f, g ) = ( FT[ K0 ( x, y)]) ( FT[ K0 ( x, y)]). In practice, convolution kernels are always space-limited with a squared radius denoted as R0. This certainty implies that mask patterns within a 2R0 2R0 square should have influences on intensity of the center point, while patterns outside this square have no impact at all. Frequency domain method, in its nature, is a periodic signal analysis method, and requires the mask patterns to be periodically repeated in space. To accurately evaluate intensities of an L L area, a spatial period of at least L+2R0 is needed, as illustrated in Fig. 2. In our new algorithm, a to-be-imaged square (To-be-Imaged Block, TIB) with edge length L=2R0 is chosen. A new system determined by a set of new convolution kernels {K1 i } with 2R0 as the radius is thus constructed, where {K1 i } are derived from the previous {K0 i } set by spatial expansion. A frequency domain TCC reflecting the introduction of the new system can be built by kernel sets {K1 i } in the same way as of eq. (3). Fig. 2. Periodic mask to image an L L block in frequency domain. Up to this point, to calculate intensities of a 2R0 2R0 area using frequency domain method without perceptible inconsistency with spatially convoluted results, a 4R0 4R0 mask window will be spatially repeated, and the corresponding mask Fourier Transform should be calculated before further steps. One may question about the efficiency because only the 2R0 2R0 TIB in center is useful for every 4R0 4R0 window repeating. This question will be answered in the following sub-sections. A large layout can be partitioned into many 2R0 2R0 TIBs, and this forms the basis of full-chip DSI. 2.3 Fourier transform of element block Computation of Fourier Transform of a 4R0 4R0 mask window begins with a procedure of polygon clipping on this region, and then a 2-D Fourier Transformation is performed on the clipped graphics. However, as illustrated in Fig. 3, two consecutively imaged TIBs, B1 and B2, have 8 common influencing sub-blocks, namely b3, b4, b7, b8, b11, b12, b15 and b16. Hence the computational redundancy should be able to be eliminated. Here we name every R0 R0 sub-block in Fig. 3 an Element Block (EB). The

6 538 Science in China Ser. F Information Sciences 2005 Vol.48 No Fig. 3. Share element blocks in a pipelined style. Fourier Transforms of 16 EBs within a 4R0 4R0 mask window are calculated and stored, and subsequently they can be re-used by 8 neighboring TIBs by simple kπ/2 space shifting. By this method, mask patterns clipped within any EB are only necessary to be transformed one single time; reuse of the transformed result requires only sign changes. Moreover, post-ret mask patterns can still be easily decomposed into rectangles and 45-degree right triangles with positive/negative transmissions [12] whose spectra are analytic sums of simple sinc-like functions. For example, a rectangle with point (x 0, y 0 ) on its bottom-left and (x 1, y 1 ) on top-right has Fourier Transform F(u,v) expressed in eq. (4b), where u and v are 2-D frequencies. P(u, v) = (e -2πjux1 e -2πjux0 )*(e -2πjvy1 e -2πjvy0 ), F(u, v) = C * 1/u * 1/v * P(u, v). Since lithographic process is band-limited, the needed harmonics M*M of each rectangle or triangle to be processed are not necessary at all to be many. Using look-up table (LUT) containing 2-D products of sine values on discrete points with the interval of minimum mask resolution, P(u,v) in eq. (4a) can be quickly computed by looking up the table through periodic indexing. After all P(u,v) of rectangles in an EB are summed, one multiplication of 1/u*1/v is performed for each discrete (u,v) pair. Processing of 45-degree right triangle can follow the same routine, but factor of 1/(u v) would ask for additional processing. Overall, for an EB which contains N decomposed rectangles and 45-degree right triangles and is to be transformed into M*M harmonics, (3~4)*N*M*M of table look-up operations and 3*M*M of (u,v) pair multiplications are totally needed in our new method, which is several orders faster than traditional directly-computing methods. 2.4 A specialized 2-D FFT scheme The frequency spectra of Pseudo-Intensities on a 4R0 4R0 area can be calculated according to eq. (1b) and other algorithms presented in previous parts of section 2. 2-D Inverse DFT should be used afterwards to get intensities in space domain. For each im- (4a) (4b)

7 Full-IC manufacturability check based on dense silicon imaging 539 aged window, the computation is expressed as a 2-D DFT with M*M inputs and N*N outputs, where M*M is the total harmonic number and N*N is the number of sample points in this area. The number M is determined by system bandwidth. In this case, M=4R0*NA*(1+sigma)/lambda, where NA is the numerical aperture of optical system, sigma is the partial coherence factor of illumination, and lambda the wavelength. Fast DFT approaches, especially FFT, were actually adopted by some authors in previous work on dense aerial imaging. The possibility of applying interpolation was also considered to get finer image on some spots from only M*M outputs [15 17]. In general, to use conventional zero-padding FFT to image a dense point array of size N*N, the complexity is N*N*log 2 N. Since M is typically much smaller than N, we can modify this FFT method a little to compute the over-sampled N*N outputs more quickly. In such an approach, the N*N outputs can be computed by M*M-to-M*M FFTs for (N*N)/(M*M) times totally. The complexity of this method for computing over-sampled signal is N*N*log 2 M. The speed for computing each TIB is critical because the Inverse Fourier Transforms of all partitioned TIBs occupy most of the computations for DSI of one chip layout. In the algorithmic model stated previously, we find three properties being very useful for further acceleration on each TIB: i) According to eq. (1b) and eq. (3), I(f, g)=i*( f, g), so I(x, y) is always real. ii) The 2-D DFT has M*M inputs and N*N outputs where M is much smaller than N, so this is an over-sampling case in 2-D. iii) For each window of size N*N, the desired TIB is actually the N/2*N/2 area in the center of the window. Assume there are two frequency domain signals F 1 (k) and F 2 (k), the inverse DFTs of these two signals are f 1 (n) and f 2 (n) as listed in eq. (5a). If both f 1 (n) and f 2 (n) are real, a new signal g(n), whose real part is f 1 (n) and the imaginary part is f 2 (n), can be computed by only one N-point DFT as in eq. (5b). Extending this method to 2-D case, every two TIBs on the wafer can be computed together as one TIB with complex intensities. N 1 N 1 nk 1 = 1 N 2 = 2 k= 0 k= 0 N f ( n) F( k) W, f ( n) F ( k) W, nk (5a) N 1 gn ( ) = f( n) + jf( n) = ( F( k) + jf( k)) W k = 0 We now consider the over-sampling 2-D DFT given in Fig. 4. For explanation purpose, the M*M inputs and the desired N/2*N/2 outputs are all placed at the top-left corner. The Fourier transformation of a 2-D N*N array could be divided into N horizontal nk N (5b)

8 540 Science in China Ser. F Information Sciences 2005 Vol.48 No Fig. 4. The specialized over-sampling 2-D DFT. and N vertical 1-D N-point DFTs. But for the original 2-D array in Fig. 4, most of its elements are padded zeros, while the desired outputs are only those N/2*N/2 points on the upper corner. An improved algorithm for computing this 2-D DFT, which is made up of two successive steps 1) and 2), is thus devised and illustrated in Fig. 5. This algorithm requires only (M+N/2) times of 1-D N-point DFT, and compared to 2N times in standard 2-D DFT, the speed could be nearly 4 times faster. Fig D DFTs pm < rpws tjem pm N/2 columns. Moreover, each 1-D N-point DFT in Fig. 5 has special properties that can be exploited further. First, the inputs of each N-point DFT, no matter whether horizontal or vertical, are all zeros except the first M points at one end. Second, for the N outputs of each DFT, only the first half N/2 points are of our interest. We have designed another algorithmic step to fully take advantage of these properties. Suppose there are two N-point DFTs with such special properties. The inputs of the two DFTs are X(m) and Y(m) with {m = 0,, M 1}, while the outputs are x(n) and y(n) with {n = 0,, N 1}, respectively. If we can construct a new input signal {Z(k), k = 0,, 2M 1} so that its time domain counterpart {z(n), n = 0,, N 1} is composed of half period of x(n) and half period of y(n), then the costs of computing both x(n) and y(n) can be halved. A linear system for building such a new signal z(n) is illustrated in Fig. 6. The low-pass filter and high-pass filter in Fig. 6 are implemented by two M-order FIR filters. To compute Z(k) which has totally 2M items, two 2M-point IFFTs are applied to X(m) and Y(m) respectively, then one 2M-point FFT is applied to the filtered sum.

9 Full-IC manufacturability check based on dense silicon imaging 541 Fig. 6. Building Z(k), the Fourier transform of a new signal z(n), from X(m) and Y(m). To sufficiently reduce undesired effects such as gain ripple and especially aliasing, the two filters should be designed properly, where the minimum stop-band leakage and uniform gain on pass-band are the major concerns. In Fig. 7, the frequency responses of two designed filters, namely LPF and HPF, are illustrated. Although ideal switching is not achievable by an FIR filter, these two specific filters do have small aliasing between them (<1% on stop band) and unit-gain on most of the pass-band points (<1% error from 1.0). Since the switching characteristic of FIR filter is not ideal, each transition edge of the filters may occupy P points from the total N points being computed. Hence, for z(n) element corresponding to each edge point where the gain is less than 1, a rescaling adjustment is needed. However, for a small number of points close to the stop-band, which are illustrated in Fig. 7 as totally Q points for one edge, the rescaling may enlarge the aliasing error as well. To prevent this from happening, these 4*Q points should be calculated from X(m) or Y(m) directly instead of from Z(k). Calculating Q points out of N Fig. 7. Frequency responses of the LPF and HPF in Fig. 6.

10 542 Science in China Ser. F Information Sciences 2005 Vol.48 No points from M inputs, where Q and M are much smaller than N, standard DFT approach needs 8*Q*M floating operations, which, however, could still be greatly reduced by algorithms described in ref. [18]. Following the filtering and combining algorithm above, the original two M-to-N DFTs can be computed by one 2M-to-N DFT along with three 2M-to-2M DFTs and a few computations on transition edges. If we consider the number of floating operations of a standard N-to-N FFT is about 4N*log 2 N, then the computational cost of the new algorithm reduces from 8N*log 2 M to about (4N+24M)* (1+log 2 M). In our dense imaging case, M is much smaller than N, and so the acceleration factor can be one value as large as 2. The specialized 2-D FFT scheme presented above works well suited for TIB with L=2R0. For a 4R0 4R0 size window, the average floating operations on each imaged point within the central 2R0 2R0 TIB are a few more than 2*log 2 M. Compared to the 2-D FFT for over-sampled signal described in the beginning of this sub-section, our new method could increase the transforming speed if at all possible of a factor near to 16 (i.e for three properties), which in turn is 16*log 2 N/log 2 M times faster than standard 2-D FFT adopted by other papers. An example is illustrated in Table 2. Table 2 Number of operations to compute a 32X32-to-512X512 2-D DFT Algorithm FLOPS Speed up Standard 2-D FFT Specialized 2-D FFT in this paper ~ Application and experiment of DSI check An application of the DSI algorithms, presented in section 2, in checking full-chip manufacturability is presented below. An important goal for RET modifications is to achieve high image contrast at the printed edges so as to minimize the CD (Critical Dimension) variation within the process window. Therefore, it is valuable being able to detect the low contrast areas quickly. The first step designed is to perform DSI on a TIB and filter out points with intensity values within a range centered around the intensity threshold from the calibrated process model. Two Sobel operators are then convoluted with image around these points to compute the horizontal and vertical intensity gradients G x and G y, which can be combined into local intensity contrast G subsequently. Due to the sparsity of points within the threshold range as well as the low complexity of Sobel operator convolution, this step takes an insignificant amount of CPU time in comparison to DSI, though huge layout data volume requires more disk access operations. All low-contrast areas in a TIB are then marked; and after stitching together neighboring TIBs, the problematic areas can be further examined later. This process repeats until all the TIBs have been examined. Fig. 8 is given here as the result of low-contrast check on post-ret layouts in Fig. 1, where the

11 Full-IC manufacturability check based on dense silicon imaging 543 Fig. 8. Distribution of low-contrast points in warning range. dark areas are composed of points with low intensity contrast. By choosing appropriately the intensity range around the threshold and contrast value for low-contrast warning, only points with noteworthy problems are shown in this figure. Verifications of this kind have been done on several UDSM and sub-100-nanometer ICs; lack of RET processing, inappropriate RET applying and the so-called side-lobes or scum [19,20], which are unaware of by commercial RET tools based on sparse points imaging, have been detected. In Table 3, an example of full chip low-contrast check based on DSI is summarized. Thanks to all algorithms presented in this paper, DSI based check on such a 1 mm 1 mm chip can be done within 24 hours. Such a speed has not been reported by others before. Area size Table 3 Summary of one full-chip DSI and low-contrast check on a 90 nm design Radius (R0) Imaging grid M N Computer type Technology Computation time 1mm 1mm 90 nm 1280 nm 10 nm < P4/1.8G ~20000 s 4 Conclusion Due to significant OPE in deep sub-wavelength photolithography process prevalent at the current and next several technology nodes, increasingly aggressive RETs have been employed to improve manufacturability and yield. The necessity of post-ret sign-off verification using DSI has been discussed and demonstrated. Innovative algorithms are reported for the several key steps of the dense silicon imaging, namely those for element block partition, fast element block transformation and a specialized 2-D FFT scheme that is many times faster. The performance improvement resulting from these algorithms makes the full-chip dense imaging a practical option for post-ret verification methodology. Additionally, a DSI based scheme for low contrast detection is proposed and demonstrated which is an important part of post-ret verification. Acknowledgements The authors thank scientists and engineers from Semiconductor Manufacturing International Corporation (SMIC) for valuable discussions and support. This work was supported by the National Natural Science

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