Pushing 193i lithography by Joint optimization of Layout and Lithography

Transcription

1 Pushing 193i lithography by Joint optimization of Layout and Lithography Peter De Bisschop Imec, Leuven, Belgium Semicon Europe Messe Dresden, Germany Lithography session October 12, 2011

2 Semiconductor-Industry Scaling trends 500 Pitch scaling Area scaling Min. Gate Pitch [nm] min. Gate Pitch SRAM bit-cell Area [µm 2 ] SRAM bit-cell area Technology Node Technology Node The Industry would like to maintain these trends PETER DE BISSCHOP 2

3 even though this implies Lithography at decreasing k NA 0.75 NA 248 nm 193 nm k NA 0.85 NA 0.93 NA 1.2 NA 0.80 NA 1.35 NA With Single Patterning 193i: Arbitrary shapes (2D) increasingly difficult/impossible Technology Node 1.35 NA 1.35 NA Even 1D Impossible New techniques and processes (e.g. DP) Increasing restrictions on allowed layouts PETER DE BISSCHOP 3

4 Illustration: 6T SRAM Electrical diagram 6T SRAM: electrical diagram Even though this electrical scheme is fixed There are several ways to make the pattern-layouts = which pattern-shapes we will print in each process layer PETER DE BISSCHOP 4

5 Illustration: 6T SRAM Layout: 2 examples WL BL PG1 PD1 gnd PU1 Vdd Active Poly Contact Metal1 Vdd PU2 PD2 PG2 BL gnd WL Tall cell Thin cell PETER DE BISSCHOP 5

6 Illustration: 6T SRAM Layout: 2 examples Active & Poly only PG1 PD1 PU1 PU2 PU1 Active Poly PD1 PD2 PU2 PG1 PG2 PD2 PG2 Both Active & Poly: 2D patterns Simplification of shapes: More uni-directional PETER DE BISSCHOP 6

7 6T SRAM Active & Poly: actual wafer images Sour ce: Y. Bordovsky (Intel), Proc. SPIE, vol (2006) Introduction of cut-mask Cut-mask approach time PETER DE BISSCHOP 7

8 Cut-mask approach: Improved Poly CD control - Logic example 2D allowed Poly CD variation in transistor area 1D & Poly-cut mask 8 2D poly 3σ Poly CD [nm] Target Poly Active Cut 3 1D poly J nm Node 20 nm Best Poly CD control: Poly = uni-directional, single pitch + Cut J108 PETER DE BISSCHOP 8

9 Poly-Gate: layout evolution summary Random 2D 2D single gate pitch Layout Restriction Node Uni-directional Single pitch Cut-mask Spacer-defined DP & Cut A similar evolution can be expected for most other line/trench-type layers PETER DE BISSCHOP 9

10 SRAM FinFet: Fin patterning Example with double Fin at PD transistor PG PD Predicted cutpattern PV band PU Target Pattern: Fin & Gate Core & Spacers Cut V. S. Basker et. al., 2010 Symposium on VLSI Technology Digest of Technical Papers, p19 PETER DE BISSCHOP 10

11 Back to (Planar) SRAM: Metal1 & the use of a Local Interconnect (LI) layer (1) no LI (2) Single LI layer (3) dual LI layer Poly Active LI1 LI2 Metal1: uni-directional Contact Metal1 Changes in integration can lead to important layout changes PETER DE BISSCHOP 11

12 Metal 1 SRAM: calculated PV band Single Patterning Negative-tone development 28 nm 22 nm Technology node (1) noli J789 J791 (2) J472 J473 J474 J450 J475 Single LI P110P90 P100P80 P90P90 P90P80 P80P80 PETER DE BISSCHOP 12

13 Metal 1: SRAM: Litho performance Single Patterning Negative-tone development 28 nm 22 nm Technology node (1) noli J789 J791 Non-calibrated OPC! (2) Single LI J472 J473 J474 P110P90 P100P80 P90P90 P90P80 P80P80 No LI: SRAM Metal1 has no SP solution beyond ~28 nm node J450 J475 PETER DE BISSCHOP 13

14 Metal1 - SRAM: Double patterning Layout without LI layer Do we obtain enough litho performance if we split the Metal1 layer? MEF > 4 and DOF@6%EL < 100 nm for 28 nm node and beyond Split layers remain bi-directional Metal1 Split Layout DP does not save the no-li Metal1 case LI becomes a must from ~28nm node onwards PETER DE BISSCHOP 14

15 Logic: Metal1 layout variations Example: XOR cell Simple XOR implementation Metal1/Contact, if no LI layer is used (& uni-directional Poly) Out = A B + A B High Metal1 density Several Splitting conflicts scenario with LI must be considered, but that leaves still several layout options open PETER DE BISSCHOP 15

16 XOR with single LI layer Poly: uni-directional Version 1: 2D patterns in Metal1 Horizontal M1 lines on grid ( gridded layout) P_M1 At the 22/20 nm node P_M1 80 nm This pattern needs to be split PETER DE BISSCHOP 16

17 XOR with single LI layer Version 1: 2D Metal1 Assume: P_M1 80 nm Stitch necessary Vertical stitch still feasible Simulated PV band (no overlay error) Overlap exists, but is ~marginal PETER DE BISSCHOP 17

18 XOR with single LI layer Version 1: 2D Metal1 Assume: P_M1 << 80 nm (e.g. 64 nm) Vertical stitch not possible (no overlap) Diagonal stitch required Simulated PV band (no overlay error) Overlap exists, but is ~marginal PETER DE BISSCHOP 18

19 XOR with single LI layer Poly: uni-directional Version 2: Metal1 is uni-directional Horizontal M1 lines on grid ( gridded layout) If M1 gaps are large enough, split is easy and offers no conflicts But: some M2 is required to complete the internal cell wiring PETER DE BISSCHOP 19

20 Uni-directional Metal 1: on-wafer example P_M1 = 80 nm Dummy M1 tracks inserted in layout Metal1 Contact 80 nm Non-calibrated OPC! Negative-tone development Uni-directional layouts are ideal to push Single Patterning to very low pitches! PETER DE BISSCHOP 20

21 XOR with dual-li layer Poly: uni-directional Version 3: Dual-layer Local Interconnect Metal1 must allow 2D patterns again Vertical M1 lines on grid ( gridded layout ) Need to ensure DPcompatibility while making individual cell layouts Simulated PV band; 20 nm node case (litho bias still to be removed) PETER DE BISSCHOP 21

22 Metal1: future & questions Is making also Metal1 uni-directonal possible/acceptable? If Metal1 remains 2D: Can DP-compatibility be enforced in all cases with a suitable set of Design Rules? LELE or SADP? SADP is attractive (overlay-performance, EOL & LWR), but can all layouts be made compatible with SADP? 15 nm hp SADP pattern examples Core mask printed with EUV C. Bencher et. al. SPIE 2011 Metal1 is one of the major Layout-Litho challenges for current and future technology nodes PETER DE BISSCHOP 22

23 Summary - The future of lithographers Future nodes will be based on a (successful) interaction between Integration architecture Litho Printability Layout choices Design Rules Manufacturability Scalability Complexity Cost Lithographers must leave their own comfort zone and interact more closely with Design and Integration PETER DE BISSCHOP 23

24 Thank you PETER DE BISSCHOP 24