Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba

Transcription

1 Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba Advanced Mask Technology Center Dresden, Germany Senior Member of Technical Staff

2 Advanced Mask Technology Center Dresden Key Facts Joint Venture of GLOBALFOUNDRIES and Toppan Photomask Leading edge mask production facility with volume production of 250nm 14nm technology Strong competence on EUV-Mask for next generation lithography Founded: 2002 More than 200 employees

3 Content Mask Market as Part of Semiconductor Market Mask Requirements by Lithography Evolution Mask Data Sizes and Write Times Quality Triangle: Resolution vs. LWR vs. Write Time Mask 3D Effects Mask Corrections: prior and post manufacturing Multilayer Defects on EUV Masks Pellicle for EUV Masks

4 Mask Market as Part of Semiconductor Market When you buy a smartphone you never think about a photomask Although they tend to be seen as just another piece in the game and mask equipments/materials are seen as a small market with only few customers photomasks make it all happen! SEMATECH, based on a review of data from: VLSI Research, Gartner Dataquest, SIA, SEMI, Techcet

5 Mask Making within Device Manufacturing Photomasks are key elements to semiconductor device manufacturing Cheap device manufacturing relies on speedy reproduction of pattern by photomasks Photomasks need to be perfect as errors are reproduced on each chip Technical requirements to photomasks are driven by tightened lithography requirements for smaller nodes Manufacturing of the perfect photomasks these days can not be achieved anymore by off-the-shelf usage of tools/processes Business perspective: Photomasks can not be build on stock Timing of wafers in fab tightly linked to mask due dates on time delivery is key! Manufacturing capacity for high-end masks limited by multi-patterning lithography mask needs per device have increased maximum yield required for maximum capacity usage

6 Mask Making within Device Manufacturing Increasing device complexity (e.g. 3D vs. 2D transistors) and multipatterning has increased number of masks per set

7 Masks vs. Lithography Roadmap Complexity of design and requirements on photomasks have strongly increased through the last technology nodes Challenges for mask manufacturing Increasingly tight control limits for mask parameters as CD, REG, OVL, defectivity time for mask manufacturing (esp. write time) increased dramatically by design complexity significant invests in pattern generators are required Reticles, Write time and the Need for Speed, EMLC 2014, SPIE Vol.9231

8 Mask Data Sizes and Write Times Mask data sizes increase per technology by increased litho complexity Write time mainly driven by: Shot count design and fracture of it e-beam pattern generator setup (e.g. current density/max. shot size) resist properties (esp. sensitivity) Reticles, Write time and the Need for Speed, EMLC 2014, SPIE Vol.9231

9 Resists: Resolution vs. LWR vs. Write Time Development and choice of resists for mask manufacturing is always a balancing of various aspects focusing on one aspects degrades the other two Resolution: - SRAF resolution - main feature resolution for EUV Line Width Roughness: - CDU - pattern fidelity - esp. important for EUV Sensitivity: - Write time

10 Resists: Resolution vs. LWR vs. Write Time However: write time can be separated out by reducing time the dose gets into the resist increased current density of e-beam leads to less time for deposition of required dose EBM9000: EB mask writer for product mask fabrication of 16nm half-pitch generation and beyond, PMJ 2014, SPIE Vol.9256

11 Multibeam Mask Writers For the future even increasing current will not resolve issue of write time The alternative: use many beams in parallel Within Multi-Beam concept, write time is decoupled from increasing shot count

12 Absorber Materials: Mask 3D Effects Photomasks absorber thickness causes deviations of properties of diffraction spectrum compared to ideal (thin) Kirchhoff mask Phenomena occurs for EUV as well as optical photomasks Lithographic Consequences: Best-focus becomes feature-dependent Bossung curves get tilted Reduces depth-of-focus in overlapping process window OPC w/ thin mask models delivers non-optimal solutions

13 Absorber Materials: Mask 3D Effects Topics for Mask Manufacturing: New mask materials need to be characterized and selected for reduced mask 3D effects Absorber profiles (height, side wall angle etc) need to be kept constant not always covered by standard metrology for mask disposal Etch into Qz during absorber over-etch becomes problematic mask-to-mask variations of 3D effects in wafer fab need to be avoided Definition of optimal EUV stack opened again for minimizing of 3D effects

14 Mask Corrections: prior and post Manufacturing General: Mask quality requirements can hardly be achieved by off-the-shelf application of processes and tools Active compensation of process imperfections or variations over time required Prior to Manufacturing: Mask process tuned per order based on known deviations Expected deviations needs to be determined prior to mask manufacturing Constant base signature correction Forward loop based on analysis of historic data and estimation of required compensation for actual order Feedback from previous attempts of same order Post Manufacturing: Status of actual mask can be assessed and then compensation is applied based on data

15 Mask Corrections: prior and post Manufacturing Prior to Manufacturing: Manipulation Step Method Approach Potential Applications Mask Data - MPC - comparable to OPC - mask design edges moved Mask Exposure - CD Map - REG Map - Exposure Dose - change dose of shots - change placement of shots - change overall exposure dose Mask Etching - End Point Time - adjust etch time based on resist data of actual mask - mask OPC minimization - mask OPC matching - compensate for spatial process footprints - compensate for design driven placement signatures - compensate for resist sensitivity variations - Compensate for process variations The tricky part is to predict all of this upfront to get 1 st attempt in spec already!

16 Mask Corrections: prior and post Manufacturing Post Manufacturing: Mask CDU and Mask REG Signature compensation by ZEISS CDC32 TM and RegC TM tools Spatially resolved pixels are introduced into Qz blank Create a transmission map over mask optimal printed mask CD Change local expansion of mask blank change of mask REG A study of closed-loop application for logic patterning, PMJ 2012, SPIE Vol.8441

17 EUV Lithography Roadmap EUV is considered as possible solution to increasingly complex lithography using 193nm immersion For EUV still many questions open until usability for high-volume manufacturing Over time, even EUV lithography gets more and more complex EUV Lithography Progress, Challenges and Outlook, EMLC 2014, SPIE Vol.9231

18 EUV Mask Manufacturing Main differences to optical mask manufacturing: Different absorber materials Very tight requirements for CD and REG control Pattern fidelity and LWR on mask is printed on wafer due to small exposure wave length Different chemistries for cleaning/repair required Actinic mask inspection not available Actinic defect repair verification availability only starts now Special topics: multilayer defects and pellicles discussed on next slides Dedicated mask manufacturing tools required for very few customers and very few technology nodes very expensive

19 EUV Mask Blanks: Multilayer Defects In contrast to optical masks, EUV mask can have multilayer defects Defects affect mirroring behavior of multilayer and so print Multilayer defects can only hardly be found w/o actinic blank inspection only very limited capacity for actinic blank inspection available Repair strategy for these defects: Blank quality improvement Know all ML defects before mask patterning Pattern shift Compensational repair of absorber EUV masks: ready or not?, EUVL Symposium 2011

20 EUV Pellicle Pellicles are used to prevent particle fall-ons during usage For EUV pellicles have major differences to optical: Transparent at 13.5nm Withstand extreme heat introduced during exposure (up to 600 C) High stiffness during exposure Mechanical stability for de- and remount Pellicle concepts and materials still under review Industry not finally decided on when and where EUV pellicles are mandatory Likely required for logic as there one printed defect can kill the whole chip Example: ASML EUV pellicle Concept 50nm thin Si x N y or graphene films click -system for easy removal A pellicle solution for EUV, EUVL Symposium 2015

21 Summary Optical Masks: Increasing complexity of lithography increases number of masks per set Increasing mask demand at limited capacity requests very high yield even at tight mask quality control limits imposed by 14nm node requirements Powerful set of pre-/post-manufacturing process adoptions required to meet yield targets Beside yield, reducing write time is the other key to gain capacity EUV Masks: Tight requirements for resolution and pattern fidelity as wave length of 13.5nm images full mask details Resolution and increasing OPC on mask designs posses high demand on resist Limited or missing availability of actinic blank/mask inspection and defect review remains hardest challenge

22 Thank you for your Attention!