Manufacturability of computation lithography mask: Current limit and requirements for sub-20nm node

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1 Manufacturability of computation lithography mask: Current limit and requirements for sub-20nm node Jin Choi, In-Yong Kang, Ji Soong Park, In Kyun Shin, and Chan-Uk Jeon Samsung Electronics Co., Ltd, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, , Republic of Korea ABSTRACT The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub-20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area. Keywords: photomask, lithography, ILT, model based fracturing 1. INTRODUCTION The patterning resolution of lithography process is governed roughly by this well known formula, that is, Rayleigh equation. pitch λ CD = = k1, (1) 2 NA where, CD is the critical dimension of pattern which corresponds to the half pitch in case of 1:1 line and space pattern, λ is wavelength of light, and NA is numerical aperture of projection optics for lithography. According to equation (1), smaller resolution can be achieved by smaller λ and higher NA. Here, k1 value is defined by equation (1) and it represents the contrast of aerial image and the difficulty of fabrication process. Given equation (1), the process margin for wafer patterning can be understood to be decreased as the pitch of device decreases. To overcome this limit of patterning process, several candidate lithography techniques have been proposed, for example, multiple patterning technology, EUV lithography, and computational lithography, and so on. Among these lithography techniques, the computational lithography such as ILT has been attracted because it does not require additional process and expensive cost if the OPC (optical proximity correction) can obtain the accurate inverse solution and the photomask can be written accurately. Optical Microlithography XXVI, edited by Will Conley, Proc. of SPIE Vol. 8683, 86830L 2013 SPIE CCC code: X/13/$18 doi: / Proc. of SPIE Vol L-1

2 2. TRADEOFF BETWEEN MASK WRITING TIME AND DESIGN COMPLEXITY Figure 1 and 2 show the ILT design is based on the inverse ideal solution for desired wafer target and the depth of focus can be increased 2 times larger than that of conventional OPC design [1]. s Vtia#e;- target 3oititicn r"-- co C1 C2 C3.+ C4 ILT (Maw" Con wactiond Figure 1. Mask design of ILT and conventional OPC for contact printing in wafer Figure 2. Benefit of ILT technique in view point of depth of focus The photomask for high end device is usually manufactured by the e-beam writer with variable shaped beam (VSB) mode because of high writing speed and fine patterning resolution. Because the VSB mode can generate only one rectangular or triangular beam at each shot, we can understand the ILT design has the special meaning for mask manufacturing. As shown in Fig. 1, the mask design of ILT is composed of rounded or angled pattern, many number of assist feature, and very small assist patterns. The rounded or angled pattern of ILT design should be segmented finely by fracturing step, so that the number of shot increases explosively. The total writing time of VSB mask writer is calculated by the equation (2) based on current density, dose, number of shot, etc. D Mask writing time = N where, N S : Number of shot N P : Number of pass D: Dose (uc/cm2) J: Current density (A/cm2) t s : Settling time of deflector (nsec) t o : Overhead time (stage movement, etc.) S N P ( N P + t J s ) + t o (2) Proc. of SPIE Vol L-2

3 Here, we have introduced the shot complexity S and this can reduce above formula of writing time into simple equation [2]. S = (NI / NR ) (n / 0.5) (3) Mask writing time = {T N (N I / N = (T S)+t N o R ) (n / 0.5)}+ t o (4) where, T N : Normal writing time (at reference design) N I : Average shot count of interest mask in unit area N R : Average shot count of reference design in unit area n: pattern density Reference design: Net lines with 50% pattern density The shot complexity S is defined by the average shot count of interest design with respect to the 50 percent net line and we also added the effect of pattern density, n. The SEM images of figure 3 shows the examples on shot complexities of ILT designs for contact printing S=6.3 s 000'0 0141` n00-1 ooç..1j01 Figure 3. Shot complexity and SEM image of ILT design for contact printing Based on equation 4, total mask writing time becomes the function of shot complexity and writer throughput. In case of 100A current density and 70nsec settling time, the mask writing time of 15nm device node becomes about 40 hours at shot complexity of 4. Figure 4. Mask writing time according to half pitch of device and shot complexity (S) In case of 800A current density, the writing time decreases and shorter than 24hours. This means the shot complexity of 12 is acceptable and the complex ILT mask can be realizable. However, if the pattern density is considered we can understand the mask writing is still big problem for ILT manufacturing. Proc. of SPIE Vol L-3

4 (a) Conditionl: J= 800A/cm2, ts=l0nsec -e-s=1-0-s=4 O S=6 S=9 ts=12 S =12 case is realistic! HP (nm) (b) % density -0-40% density O 50% density -O 60% density x-70% density HP (nm) Figure 5. Mask writing time according to shot complexity (S) and pattern density (n) 3. MODEL-BASED FRACTURING AND ITS VERIFICATION ISSUE In recent, many EDA (Electronic design automation) companies for mask data handling and some institutes have proposed the data handling techniques for shot number reduction as efficient fracturing method [3]. Here, we will call that technology as model based fracturing, simply as MBF. Ideal curvilinear S shots S shots S shots r <Benefit of overlap shot > Shot # optimization by overlap shot S shots d u ro = Ó Overlap size i Figure 6. Shot number reduction by model based fracturing technique. Based on model based fracturing we have confirmed that the ideal curvilinear pattern can be optimized from shot complexity of 23.6 to 9.9 complexity by using overlap shot and they have the same patterning performance in mask and wafer plane. Because model based fracturing is totally different approach for conventional data fracturing, there are many issue points for the realization of that technology. One of the big problems is how to convert the design target and how to guarantee the quality of the converted result. The conventional fracturing result can be checked by XOR Boolean operation as verification step. However, the design data of MBF is generated, rather than fractured, by targeting desired mask or wafer pattern. Furthermore, small edge error of high spatial frequency should be accepted for the tolerance of the shot optimization [4]. Given these background, here, we propose new data flow for model based fracturing, as shown in figure 7. Proc. of SPIE Vol L-4

5 CAD data OPC* Verification Fracturing MBF* Mask model A XOR verification e -beam writing -> MPV* I Measurement & Inspection Figure 7. Data flow for model based fracturing. Conventional data flow for mask writing is straightforward. CAD data is processed by optical proximity correction (OPC) and OPC verification. The OPCed design is fractured for e-beam writing and checked by XOR verification. On the other hand, the model based fracturing should use different data flow. At first, accurate mask model should be prepared for model based fracturing. Then the optimized result by MBF should be verified. This is model based pattern verification (MPV) step. The result of manufactured mask should be checked by measurement and inspection, and the information should be feed backed into mask model and model based fracturing step. To make MBF efficiently, the information on inefficiency of MBF should be transferred to OPC and OPC verification step. According to this data flow it is possible to think following 4 items should be developed for the manufacturability of ILT mask. For the ILT mask we should considered what the best choice as the mask design is; segmented design or ideal diagonal design. Second, while we accept a reasonable EPE (edge placement error) for shot optimization, how can we verify the MBF result with satisfactory accuracy? Third, MBF and MPV are based on the function to predict the mask pattern by using mask model, so that the model accuracy and its coverage range should be considered. Fourth, since the ILT corresponds to the inverse solution for the desired wafer target, various kinds of assist feature should be patterned and the fidelity and resolution is the important performance for ILT. a. Target design consideration for ILT Based on numerical calculation, we have compared the accuracy between segmented diagonal design and ideal diagonal design as the target for model based fracturing. The convolution calculation, as explained in figure 8, proves that the ideal target design has smaller patterning error due to the mask model error than segmented diagonal case. Proc. of SPIE Vol L-5

6 Target design Segmented design, Ds(x) MINAC(x) Mask contour S DI NAC(x) MAC(x) > Mask contour SDAC(x) A Diff1 MINAC(x): Inaccurate mask model MAC(x): Accurate mask model MAC(x): MINAC(x) + Q(x) Ds(X) MINAC(x) = MBF1(x) Qx MINAC(x) + R1 SDAC(x) = Ds(X) MAC(x) SFAC(x) = MBF1(x) Qx MAC(x) MBF1 + R1 (residual) Optimization MAC(x) V Mask contour SFAC(x) Diff1 = SFAC(x) - SDAC(x) _ {MBF1(x)- Ds(X)} MAC(x) _ {MBF1(x) Q Q(x)} -{Ds(X) Q Q(x)} - R1 Target design Ideal curvilinear, Dc(x) MBF2 + R2 (residual) Optimization MAC(x) > D iff2 V Mask contour IFAC(x) D c(x) = MBF2(x) Qx MINAC(x) + R2 IFAC(x) = MBF2(x) Qx MAC(x) D iff2 = IFAC(x) - Dc(x) = MBF2(x) Qx MAC(x) - Dc(x) _ {MBF2(x) Q Q(x)} - R2 <Diff1>- <Diff2> _ <Ds(x) Q Q(x)> : Positive If, <MBF1(x) O Q(x)> _ <MBF2(x) O Q(x)> <R1>= <R2> Figure 8. MBF accuracy estimation according to target designs Second thing is how to verify the MBF converted data from ideal diagonal design and the mask patterning result. Like conventional mask process, design data is converted by MDP software but special verification algorithm should be added in mask plane verification and wafer plane verification. The obtained e-beam data is used for mask writing and the mask pattern quality is checked by SEM measurement and inspection tools. Design Mask Data Prep (using MBF) Simulation Mask writing SEM measurement Inspection Mask pattern Simulation Aerial image simulation Shot number, Writing time, Beam stability CD unif, CD contour, Model verify Die -to -die Inspection w.r.t. reference Verification-7 Figure 9. Process flow for ILT mask manufacturing Here, we propose the aerial image simulation of mask scale as new verification method of MBF result for ILT mask. Because the edge placement error become ambiguous criteria in case of MBF due to the patterning tolerance for shot optimization, we have used the aerial image simulation for verification. Compared with the aerial image simulation of wafer scale, the mask scale aerial image simulation is higher sensitive and if the aerial image difference is defined as AID of figure 10, we can obtain the mask scale simulation is about 40% higher sensitive, as shown in figure 10. Proc. of SPIE Vol L-6

7 Ideal design Segmented design Il II AI: Aerial image II: AI(ideal design) II +1: AI(ideal Biased +1nm) II_l: AI(ideal Biased -1nm) ref: II +1- II Is,h: AI(segmented height h) AID=Is,h- II /Iref : Normalized Al difference o Step height (nm) 100 Figure 10. Advantage of mask scale aerial image simulation Because model based fracturing and model based pattern verification are based on model accuracy, the required accuracy and the effect of model error have been considered. If the mask model is assumed to be multiple Gaussian functions and mask patterning process is linear system, the patterning effect due to mask model error gives rise to size error at corner and edge according to the relation between pattern shape and interaction range of model. PSF of mask model : F exp(- (x/sigmashort) ^2) + ï exp(- (x/sigma1ony) ^2) where, Sigmashort < D2 < Sigma1oy is assumed Target Mask contour 1) If Sigmashort has error 2) If Sigma1o9 has error Figure 11. Effect on mask pattern simulation due to mask model error At a specific pattern of ILT we have obtained the model sensitivity on CD error due to model error is about CD error of 0.5nm per 3% model error. Because the ILT design corresponds to the inverse solution for the desired wafer target, the ILT design could have many and small assist features. Here, we have defined the effectiveness E of assist feature as the total intensity of the aerial image with respect to the target area. Figure 12 shows the effectiveness E rapidly decreases as the pattern size decreases. This graph shows the smaller assist feature than 35nm is not effective, so that OPC should consider the balance between the effectiveness of assist feature and the burden on photomask patterning. Proc. of SPIE Vol L-7

8 Al: Aerial image Effectiveness of assist feature at OPC, E E = F I AI(x,y) ktarget area x n) where, n is normalization coefficient Mask pattern size (nm) AI(x,y) of single contact 90nm size 60nm size 30nm size Figure 12. Effectiveness of assist feature with respect to the pattern size In last year the idea for resolution improvement of ILT design has been reported by our group. By using overlap shot at the design edge and corner we can obtain the improved patterning resolution [5]. c,--,,,- :.T%`. m Dose increase Conventional VSB writing Improvement by overlap shot Figure 13. Pattern fidelity improvement of ILT design by overlap shot Until now we have discussed about the required development items for ILT mask patterning. Now, let s consider the manufacturing possibility of ILT mask that means allowable manufacturing area and requirements for future. Considering writing time (<24 hours) and computation limit on convolution the current ILT manufacturing have the limit of application area. Proc. of SPIE Vol L-8

9 for MBF or MPV PAl$ei'% area (iiiritz) Figure 14. (a) Allowable max. shot complexity within 24hr writing time and (b) Estimated computation time for MBF or MPV. In figure 14(a) the x axis and y axis show pattern density and the shot complexity, respectively. By the writing time calculation, the dot graph of figure 14(a) represents the 24 hour writing time. Because ILT design uses high shot complexity, the allowable pattern density exists. Here, the pattern density is defined by the pattern area divided by total area. On the other hands, the MBF and MPV are based on convolution calculation between pattern designs and mask model. Considering the computation time for the convolution, we can understand the allowable pattern area also exists. This means the total area of ILT application in full chip is limited. To increase the application area in full chip the high throughput writer and computation method for full-chip should be developed SUMMARY Computational lithography technique has many benefits such as improvement of the margin for wafer patterning process. However, there is tradeoff relation between mask writing time and design complexity. Here, for ILT mask manufacturing, we have proposal new data flow which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT mask is shown to have the limit of application area. Based on these, high throughput writer and computation method for full-chip should be developed for the ILT-manufacturability of full chip design REFERENCES [1] B. G. Kim, et. al., Trade-off between Lithographic Performance and Mask Cost of Masks made by Inverse Lithography Technology, SPIE 7379, 73791M (2009) [2] Jin Choi et. al., E-beam Shot Count Estimation at 32 nm HP and Beyond, SPIE Vol. 7379, (2009). [3] Chua, G. S., Wang, W. L., Choi B. I., Zou, Y., Tabery, C., Bork, I., Nguyen, T., Fujimura, A., Optimization of mask shot count using MB-MDP and lithography simulation, SPIE, Vol. 8166, (2011) [4] H. Tanabe, et. al., LER transfer from a mask to wafers, SPIE Vol. 6607, 66071H (2007). [5] B. G. Kim, et. al., Improving CD uniformity using MB-MDP for 14nm node and beyond, Proc. SPIE. 8522, (2012) Proc. of SPIE Vol L-9